CN-122019427-A - Accelerated QLC write digital stream management device and memory controller chip

CN122019427ACN 122019427 ACN122019427 ACN 122019427ACN-122019427-A

Abstract

The invention belongs to the technical field of storage controllers and provides an acceleration QLC write digital stream management device and a storage controller chip, wherein the device comprises a data DMA, a write command analysis and distribution module and a buffer release management module, wherein the data DMA is used for copying data to be written into a target buffer area and feeding back to the write command analysis and distribution module after copying is completed to update a data buffer state table, the write command analysis and distribution module is used for taking out a control word from a control word queue, taking out a corresponding write command from the write command queue according to the control word and configuring the data DMA, adding a release command into the release command queue after the copying is known, and the buffer release management module releases the corresponding buffer according to the data buffer state table. The accelerating QLC write data stream management device provided by the invention can reduce the complexity of QLC particle write command processing, improve the execution efficiency of write commands, reduce the loss of firmware processing during multiple writing and reduce the occupation of CPU.

Inventors

ZHANG LEI
WANG DAN
ZHANG DONGFENG
ZHUO YUE

Assignees

合肥大唐存储科技有限公司

Dates

Publication Date: 20260512
Application Date: 20260128

Claims (7)

1. An accelerating QLC write digital stream management device is characterized by comprising a data DMA, a write command analysis and distribution module and a buffer release management module, The data DMA is used for copying the data to be written into the target cache area, and feeding back to the writing command analysis and distribution module to update the data cache state table after the copying is completed, wherein the data in the target cache area is read when the data is written for the second time; The write command analysis and distribution module is used for taking out control words from the control word queue, taking out corresponding write commands from the write command queue according to the control words, configuring data DMA according to the control words, and adding release commands to the release command queue after knowing that copying is completed; and the buffer release management module takes out a release command according to the data buffer state table to release the corresponding buffer.
2. The apparatus of claim 1, wherein the write command parsing distribution module determines whether to fetch a corresponding write command in the write command queue based on a write mode field in the control word, The write command analysis and distribution module configures the data DMA to copy the data to be written into the target buffer area according to the write mode field in the control word, wherein the write mode field comprises immediate execution, starting at the first write time and starting after the first write time.
3. The apparatus of claim 2, wherein the data to be written is copied from the source buffer to the destination buffer, the data in the source buffer being read for the first time.
4. The apparatus of claim 3, wherein the fields in the data cache state table include a copy complete flag and a cache address, wherein the copy complete flag is used to indicate whether the copying of the data is complete, updated by the write command resolution distribution module, and the cache address is used to indicate a storage address of the data to be written.
5. The apparatus of claim 4, wherein the source buffer and the destination buffer are respectively preset areas in RAM, and the write direction field in the control word comprises SRAM-to-DRAM, SRAM-to-SRAM, DRAM-to-DRAM.
6. The apparatus of claim 1, wherein the fields in the release command include a release command number, a release address, and a release length.
7. A memory controller chip comprising the accelerated QLC write digital stream management device of any one of claims 1 to 6.

Description

Accelerated QLC write digital stream management device and memory controller chip Technical Field The invention relates to the technical field of memory controllers, in particular to an acceleration QLC write digital stream management device and a memory controller chip. Background For the QLC memory grain, because of the requirement of the method of use thereof, two write operations to the QLC memory grain need to be performed for the same batch of data to be written to the QLC grain. When QLC storage particles are used, data from the host needs to be written twice to be stored in the particles. The existing memory control chip is insufficient in support of twice writing functions in design, so that the time for writing data is long, and the data throughput rate of the memory control chip is affected. If two writes are directly waiting for completion, the memory control chip will have a significantly longer time to process each write, which reduces the processing bandwidth of the host. Disclosure of Invention Aiming at the defects in the prior art, the invention provides an accelerating QLC write digital stream management device and a memory controller chip, so as to solve the problem that the time delay is caused by waiting for the completion of two writing operations when the current data is written into QLC memory particles. In a first aspect, the present invention provides an accelerated QLC write digital stream management apparatus, including a data DMA, a write command parsing and distributing module, and a buffer release management module, The data DMA is used for copying the data to be written into the target cache area, and feeding back to the writing command analysis and distribution module to update the data cache state table after the copying is completed, wherein the data in the target cache area is read when the data is written for the second time; The write command analysis and distribution module is used for taking out control words from the control word queue, taking out corresponding write commands from the write command queue according to the control words, configuring data DMA according to the control words, and adding release commands to the release command queue after knowing that copying is completed; And the buffer release management module takes out the buffer command according to the data buffer state table and releases the corresponding buffer. According to the technical scheme, the accelerating QLC write digital stream management device provided by the invention ensures that the storage grain controller can obtain effective write data during two times of writing through data copying and state control, reduces the complexity of processing QLC grain write commands, improves the execution efficiency of the write commands, and simultaneously reduces the loss during firmware processing for multiple times of writing and reduces the occupation of a CPU. Optionally, the write command parsing and distributing module decides whether to fetch the corresponding write command in the write command queue according to the write mode field in the control word, The write command analysis and distribution module configures the data DMA to copy the data to be written into the target buffer area according to the write mode field in the control word, wherein the write mode field comprises immediate execution, starting at the first write time and starting after the first write time. Optionally, the data to be written is copied from the source buffer to the destination buffer, and the data in the source buffer is read when being written for the first time. Optionally, the fields in the data cache state table include a copy completion flag and a cache address, where the copy completion flag is used to indicate whether the data copy is completed, and the cache address is used to indicate a storage address of the data to be written. Optionally, the source buffer area and the destination buffer area are respectively preset areas in the RAM, and the writing direction field in the control word comprises SRAM-to-DRAM, SRAM-to-SRAM, DRAM-to-SRAM and DRAM-to-DRAM. Optionally, the fields in the release command include a release command number, a release address, a release length. In a second aspect, the present invention provides a memory controller chip, including an accelerated QLC write digital stream management device according to any one of the possible implementation manners of the first aspect. By adopting the technical scheme, the application has the following beneficial effects: The invention ensures that the storage grain controller can obtain effective writing data during two times of writing through data copying and state control, reduces the complexity of QLC grain writing command processing, improves the execution efficiency of writing commands, and simultaneously reduces the loss during multiple times of writing of firmware processing and reduces the occupation of CPU by using the writing data flo