CN-122019431-A - Circuit and method for direct memory access using network on chip

Abstract

The present application provides circuits and methods for direct memory access using a network on chip. A configurable integrated circuit includes a network on chip and a response buffer circuit coupled to the network on chip. The response buffer circuit includes a direct memory access circuit and a controller circuit. The direct memory access circuit generates read requests and write requests to access the memory circuit. The controller circuit provides the read request and the write request to the memory circuit over the network on chip. The controller circuit exchanges data for read requests and write requests with the memory circuit.

Inventors

• Tara Sylvaikar
• WEBB SCOTT
• LU ZHIHENG
• Jarrod blackburn
• Ian Hansen

Assignees

• 阿尔特拉公司

Dates

Publication Date

20260512

Application Date

20251010

Priority Date

20241112

Claims (20)

1. 1. A configurable integrated circuit, comprising: A first network-on-chip, and A response buffer circuit coupled to the first network-on-chip, wherein the response buffer circuit comprises a direct memory access circuit and a controller circuit, wherein the first network-on-chip is embedded in the configurable integrated circuit, wherein the direct memory access circuit generates a first read request and a first write request received from a host circuit to access a first memory circuit, wherein the controller circuit provides the first read request and the first write request to the first memory circuit through the first network-on-chip, and wherein the controller circuit exchanges first data for the first read request and the first write request with the first memory circuit.
2. 2. The configurable integrated circuit of claim 1, wherein the first memory circuit comprises a block random access memory in the configurable integrated circuit.
3. 3. The configurable integrated circuit of any of claims 1-2, wherein the first memory circuit comprises a memory external to the configurable integrated circuit in at least one die stacked in a vertical direction with the configurable integrated circuit.
4. 4. The configurable integrated circuit of any of claims 1-2, wherein the direct memory access circuit comprises a command first-in first-out circuit that stores descriptors of read transactions and write transactions, and wherein the direct memory access circuit further comprises a finite state machine that uses the descriptors of the read transactions and the write transactions to generate the first read request of the read transactions and the first write request of the write transactions.
5. 5. The configurable integrated circuit of any one of claims 1 to 2, wherein the direct memory access circuit comprises a control status register circuit that stores status, error, suspend, and reset information for a read transaction corresponding to the first read request and a write transaction corresponding to the first write request.
6. 6. The configurable integrated circuit of claim 5, wherein the control state register circuit comprises a content addressable memory that stores an address of an error, an error type of any error, a completion status, and a unique identifier in each of the read transaction and the write transaction.
7. 7. The configurable integrated circuit of any one of claims 1 to 2, wherein the direct memory access circuit comprises an error monitor circuit that polls an incoming signal for errors in transactions comprising the first read request and the first write request and forwards the errors to a storage circuit for storage.
8. 8. The configurable integrated circuit of any of claims 1 to 2, further comprising: a second network-on-chip coupled to the response buffer circuit, wherein the controller circuit provides a second read request and a second write request to a second memory circuit through the second network-on-chip, and wherein the controller circuit exchanges second data for the second read request and the second write request with the second memory circuit.
9. 9. The configurable integrated circuit of claim 8, wherein the second memory circuit comprises a memory external to the configurable integrated circuit in at least one die peripheral to the configurable integrated circuit.
10. 10. A method for performing read transactions and write transactions in a configurable integrated circuit, the method comprising: generating, using a direct memory access circuit in the configurable integrated circuit, a read request for a read transaction and a write request for a write transaction for accessing a memory circuit; providing the read request and the write request from the direct memory access circuit to the memory circuit over a first network-on-chip in the configurable integrated circuit using a scheduler circuit in the configurable integrated circuit, and Data for the read request and the write request is circuit-switched with the memory using the scheduler circuitry.
11. 11. The method of claim 10, further comprising: A response to a status query for one of the read transaction or the write transaction is sent from the direct memory access circuit over a second network-on-chip in the configurable integrated circuit, the response including an error value, a tag to confirm that the response is for one of the read transaction or the write transaction from the direct memory access circuit, a fill level of a command first-in-first-out circuit in the direct memory access circuit that stores descriptors of the read transaction and the write transaction, or a completion status of one of the read transaction or the write transaction.
12. 12. The method of any of claims 10 to 11, wherein the memory circuit is located in a die stacked in a vertical direction with the configurable integrated circuit, and wherein the read transaction and the write transaction are three-dimensional transactions to and from the die.
13. 13. The method of any of claims 10 to 11, further comprising: A read identifier tracking mechanism is used to track one of the read transactions by tracking the returned read response and mapping the read response to one of the read requests to allow a user to write to any addressable memory within the memory bank.
14. 14. The method of any of claims 10 to 11, wherein generating the read request for the read transaction and the write request for the write transaction further comprises: Descriptors of the read transactions and the write transactions are stored in a command first-in first-out circuit in the direct memory access circuit, wherein the descriptors are configurable by a user to handle transaction synchronization, interleaving, and memory stride.
15. 15. The method of any of claims 10 to 11, further comprising: storing descriptors of the read transaction and the write transaction in a first-in first-out circuit in the direct memory access circuit, and The descriptors are processed using a finite state machine in the direct memory access circuit to generate the read request for the read transaction and the write request for the write transaction.
16. 16. A non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by a configurable integrated circuit, cause the configurable integrated circuit to: Generating a read request and a write request to access the memory circuit using the direct memory access circuit; Providing the read request and the write request from the direct memory access circuit to the memory circuit over a network on chip using a controller circuit, and Data for the read request and the write request is exchanged with the memory circuit using the controller circuit.
17. 17. The non-transitory computer-readable storage medium of claim 16, wherein the instructions further cause the configurable integrated circuit to: Status, error, suspend, and reset information of a read transaction corresponding to the read request and a write transaction corresponding to the write request are stored in a control status register circuit in the direct memory access circuit.
18. 18. The non-transitory computer-readable storage medium of any of claims 16-17, wherein the instructions further cause the configurable integrated circuit to: Storing descriptors of the read transaction and the write transaction in first-in-first-out circuitry in the direct memory access circuitry; providing the descriptor to a finite state machine in the direct memory access circuit, and The descriptors of the read transaction and the write transaction are processed using the finite state machine to generate the read request of the read transaction and the write request of the write transaction.
19. 19. The non-transitory computer-readable storage medium of any of claims 16-17, wherein the instructions further cause the configurable integrated circuit to: Polling an incoming signal using an error monitor circuit in the direct memory access circuit for errors in transactions including the read request and the write request, and The error is forwarded to a storage circuit for storage.
20. 20. The non-transitory computer-readable storage medium of any of claims 16-17, wherein the instructions further cause the configurable integrated circuit to: Data for the read request and the write request is circuit-exchanged with the memory via the network-on-chip using the controller circuit, wherein the network-on-chip is located in the configurable integrated circuit.

Description

Circuit and method for direct memory access using network on chip Technical Field The present disclosure relates to circuits and methods for direct memory access using a network on chip. Background A configurable Integrated Circuit (IC) may be configured by a user to implement desired custom logic functions. In a typical scenario, logic designers use Computer Aided Design (CAD) tools to design custom circuit designs. When the design process is complete, the computer aided design tool generates an image containing the configuration data bits. The configuration data bits are then loaded into configuration memory elements that configure configurable logic circuits in the integrated circuit to perform the functions of the custom circuit design. Disclosure of Invention In one aspect, an embodiment of the application provides a configurable integrated circuit comprising a first network-on-chip, and a response buffer circuit coupled to the first network-on-chip, wherein the response buffer circuit comprises a direct memory access circuit and a controller circuit, wherein the first network-on-chip is embedded in the configurable integrated circuit, wherein the direct memory access circuit generates a first read request and a first write request received from a host circuit to access the first memory circuit, wherein the controller circuit provides the first read request and the first write request to the first memory circuit through the first network-on-chip, and wherein the controller circuit exchanges first data for the first read request and the first write request with the first memory circuit. In another aspect, embodiments of the present application provide a method for performing read transactions and write transactions in a configurable integrated circuit, the method comprising generating read requests for read transactions and write requests for write transactions for access to a memory circuit using a direct memory access circuit in the configurable integrated circuit, providing the read requests and the write requests from the direct memory access circuit to the memory circuit over a first network-on-chip in the configurable integrated circuit using a scheduler circuit in the configurable integrated circuit, and exchanging data for the read requests and the write requests with the memory circuit using the scheduler circuit. In yet another aspect, embodiments of the present application provide a non-transitory computer-readable storage medium including instructions stored thereon that, when executed by a configurable integrated circuit, cause the configurable integrated circuit to generate read requests and write requests to access a memory circuit using a direct memory access circuit, provide the read requests and the write requests from the direct memory access circuit to the memory circuit over a network on chip using a controller circuit, and exchange data for the read requests and the write requests with the memory circuit using the controller circuit. Drawings Fig. 1 is a diagram illustrating a microarchitecture of a portion of an Integrated Circuit (IC) including a master network-on-chip (MNOC), a response buffer circuit including Direct Memory Access (DMA) circuits, and a microchip network-on-chip (uNOC). Fig. 2A is a diagram illustrating an example in which a host performs a status query by sending a read request to a response buffer circuit along with an initial write request and write data. Fig. 2B is an example illustrating a host performing a status query using a push/push write request to a localized mailbox. FIG. 3 is a diagram illustrating an example of a system in which a host sends a descriptor to the DMA circuit of FIG. 1, then sends a status request for a transaction, and finally receives a status response. Fig. 4 is a diagram illustrating states of a Finite State Machine (FSM) in the FSM circuit of fig. 1 and examples of transitions between the states. FIG. 5 is a diagram illustrating components in a structural sector of an Integrated Circuit (IC) that may implement read and write transactions to memory. Fig. 6 is a diagram illustrating an example of a system that may be used for two-dimensional (2D) read or write applications. Fig. 7 is a diagram illustrating an example of a system that may be used for three-dimensional (3D) read or write applications. Fig. 8 is a diagram of an illustrative example of a configurable Integrated Circuit (IC). Fig. 9A illustrates a block diagram of a system that may be used to implement a circuit design programmed into a programmable logic device using design software. Fig. 9B is an illustration depicting an example of a programmable logic device including a structural die and a base die coupled to each other by micro bumps. FIG. 10 is a block diagram illustrating a computing system configured to implement one or more aspects of the embodiments described herein. Detailed Description In certain types of previously known configurable Integrated Circuits (