CN-122019433-A - Data processing method, device and storage medium

CN122019433ACN 122019433 ACN122019433 ACN 122019433ACN-122019433-A

Abstract

The application discloses a data processing method, a device and a storage medium, which relate to the technical field of data processing and disclose the data processing method, wherein the data processing method comprises the steps of acquiring a target protocol type, a target data bit width and a target sampling mode corresponding to a data transmission request in a register when the data transmission request is received; sampling the input serial data of the target protocol type based on the target sampling mode and a sampling clock corresponding to the data transmission request to obtain sampling data, generating a data frame based on the sampling data and the target data bit width, and writing the data frame into an asynchronous first-in first-out queue based on the sampling clock. The application realizes compatibility of multiple protocols, multiple bit widths and multiple modes under the same hardware architecture.

Inventors

HUANG YU
ZHANG GONG
ZHANG YONG
WANG RIYAN
HE HONGYIN
YANG KUNMING

Assignees

广州润芯信息技术有限公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (10)

1. A data processing method, characterized in that the data processing method comprises: When a data transmission request is received, acquiring a target protocol type, a target data bit width and a target sampling mode corresponding to the data transmission request from a register; sampling the input serial data of the target protocol type based on the target sampling mode and a sampling clock corresponding to the data transmission request to obtain sampling data; Generating a data frame based on the sampled data and a target data bit width; Based on the sampling clock, the data frame is written into an asynchronous first-in first-out queue.
2. The data processing method as claimed in claim 1, wherein the step of sampling the input serial data of the target protocol type based on the target sampling pattern and a sampling clock corresponding to the data transmission request, to obtain the sampled data comprises: Acquiring a system master clock corresponding to an upper computer; performing frequency division operation on the system master clock based on the sampling frequency corresponding to the data transmission request to obtain a sampling clock; And based on the target sampling mode and the sampling clock, sampling the input serial data of the target protocol type to obtain sampling data.
3. The data processing method of claim 2, wherein the step of sampling the input serial data of the target protocol type based on the target sampling pattern and the sampling clock to obtain the sampled data comprises: if the target sampling mode is a single edge mode, sampling the input serial data at the rising edge of the sampling clock to obtain sampling data; and if the target sampling mode is a double-edge mode, sampling the input serial data on the rising edge and the falling edge of the sampling clock respectively to obtain sampling data.
4. The data processing method of claim 1, wherein the step of generating a data frame based on the sampled data and a target data bit width comprises: writing the sampling data into a shift register; And generating the data frame based on the sampling data in the shift register when the sampling data in the shift register reaches the target data bit width.
5. The data processing method of claim 4, wherein the step of generating the data frame based on the sampled data in the shift register comprises: acquiring the number of the lanes corresponding to the data transmission request; the data frame is generated based on the lane number and the sample data in the shift register.
6. The data processing method of claim 1, wherein the step of writing the data frame to an asynchronous fifo queue based on the sampling clock comprises: generating a frame synchronizing signal based on the sampling clock, wherein the rising edge of the frame synchronizing signal is synchronous with the rising edge of the sampling clock corresponding to the first sampling result in the data frame; the data frame is written into an asynchronous first-in first-out queue based on the frame synchronization signal.
7. The data processing method according to any one of claims 1 to 6, wherein when the data transmission request is received, before the step of acquiring the target protocol type, the target data bit width, and the target sampling pattern corresponding to the data transmission request in the register, the data processing method further comprises: when a configuration instruction of an upper computer is received, acquiring a plurality of protocol type information, a plurality of data bit width information and a plurality of sampling mode information corresponding to the configuration instruction; And writing the protocol type information, the data bit width information and the sampling mode information into a register respectively.
8. The data processing method of claim 7, wherein the protocol type information includes at least SSI protocol, mcBSP protocol, I2S protocol, the data bit width information includes at least 16 bits, 24 bit, and 48 bits, and the sampling mode information includes single-edge SDR mode and double-edge DDR mode.
9. A data processing apparatus comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the computer program being configured to implement the steps of the data processing method according to any one of claims 1 to 8.
10. A storage medium, characterized in that the storage medium is a computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, realizes the steps of the data processing method according to any one of claims 1 to 8.

Description

Data processing method, device and storage medium Technical Field The present application relates to the field of data processing technologies, and in particular, to a data processing method, apparatus, and storage medium. Background With the increasing complexity of radio frequency communication systems, audio interfaces, and on-chip multiprotocol data channels, digital chips are required to simultaneously support multiple common data transmission protocols, such as SSI (Synchronous SERIAL INTERFACE ), mcBSP (Multichannel Buffered Serial Port, multi-channel buffered serial port), I2S (Inter-IC Sound), and the like. Conventional practice typically designs a set of transmit and receive logic for each protocol independently, including independent clock generation, shift registers, frame synchronization and control circuitry. This approach, while simple to implement, can result in significant duplication of logic resources, especially when protocol differences are defined only in frame format or bit width, the shifted sampling units tend to be structurally similar, resulting in an unnecessary increase in area and power consumption. Furthermore, different protocols have different requirements for data bit width and transmission mode. If multiple sets of hardware logic are adopted, resources cannot be shared among all channels, and dynamic switching is difficult to realize in the same interface. The designer needs to constrain each interface unit separately during the integration and layout stages, which introduces more complex timing management problems. For the multi-rate communication scene, when the frequency of the main clock is increased, the timing margin of the serial-parallel conversion unit is reduced, edge sampling errors are easy to generate, and if the serial-parallel conversion unit is independently designed, each interface needs to be re-verified, so that the verification workload is further increased. Therefore, how to realize compatibility of multiple protocols, multiple bit widths and multiple modes under the same hardware architecture is a problem to be solved. The foregoing is provided merely for the purpose of facilitating understanding of the technical solutions of the present application and is not intended to represent an admission that the foregoing is prior art. Disclosure of Invention The application mainly aims to provide a data processing method, a data processing device and a storage medium, and aims to solve the technical problem of how to realize compatibility of multiple protocols, multiple bit widths and multiple modes under the same hardware architecture. In order to achieve the above object, the present application provides a data processing method, including: When a data transmission request is received, acquiring a target protocol type, a target data bit width and a target sampling mode corresponding to the data transmission request from a register; sampling the input serial data of the target protocol type based on the target sampling mode and a sampling clock corresponding to the data transmission request to obtain sampling data; Generating a data frame based on the sampled data and a target data bit width; Based on the sampling clock, the data frame is written into an asynchronous first-in first-out queue. In an embodiment, the step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock corresponding to the data transmission request, and obtaining the sampled data includes: Acquiring a system master clock corresponding to an upper computer; performing frequency division operation on the system master clock based on the sampling frequency corresponding to the data transmission request to obtain a sampling clock; And based on the target sampling mode and the sampling clock, sampling the input serial data of the target protocol type to obtain sampling data. In an embodiment, the step of sampling the input serial data of the target protocol type based on the target sampling mode and the sampling clock, and obtaining the sampled data includes: if the target sampling mode is a single edge mode, sampling the input serial data at the rising edge of the sampling clock to obtain sampling data; and if the target sampling mode is a double-edge mode, sampling the input serial data on the rising edge and the falling edge of the sampling clock respectively to obtain sampling data. In one embodiment, the step of generating the data frame based on the sampled data and the target data bit width includes: writing the sampling data into a shift register; And generating the data frame based on the sampling data in the shift register when the sampling data in the shift register reaches the target data bit width. In an embodiment, the step of generating the data frame based on the sampled data in the shift register comprises: acquiring the number of the lanes corresponding to the data transmission request; the data frame is generat