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CN-122019435-A - FPGA chip logic configuration on-line upgrading circuit and method

CN122019435ACN 122019435 ACN122019435 ACN 122019435ACN-122019435-A

Abstract

The application discloses an on-line upgrading circuit and method for logic configuration of an FPGA chip. The analog switch chip is provided with a first input channel, a second input channel and an output channel, wherein the first input channel is connected with the SPI interface of the MCU, the second input channel is connected with the configuration SPI interface of the FPGA, the output channel is connected with the SPI pin of the configuration Flash, and the gating signal is controlled by the MCU. The MCU receives configuration data and an upgrade instruction sent by an external host, controls the analog switch to switch between the MCU writing Flash and the FPGA reading Flash, writes the configuration Flash on line through the USB and loads the configuration Flash to the FPGA. The circuit can complete field upgrade without disassembling and uncovering and JTAG, and reduces maintenance cost.

Inventors

  • GENG YUNTAO
  • LIU BO
  • TANG XIAOPING

Assignees

  • 清能德创电气技术（北京）有限公司
  • 芜湖清能德创电子技术有限公司

Dates

Publication Date
20260512
Application Date
20260129

Claims (10)

  1. 1. The FPGA chip logic configuration online upgrading circuit is characterized by comprising a USB interface, a USB-to-serial port chip, a microcontroller MCU, an analog switch chip and a configuration Flash chip; The USB interface is connected with the USB end of the USB-to-serial port chip, and the serial port end of the USB-to-serial port chip is connected with the serial communication interface of the MCU; The analog switch chip is provided with a first input channel, a second input channel and an output channel, wherein the first input channel is connected with an SPI interface of the MCU, the second input channel is connected with a configuration SPI interface of the FPGA, and the output channel is connected with an SPI interface pin of the configuration Flash chip; the analog switch chip is also provided with a gating signal input end, and the gating signal input end is connected with the MCU; The MCU is used for receiving configuration data and an upgrade instruction sent by an external host through the USB interface through the serial communication interface, controlling the gating signal according to the upgrade instruction so as to write the configuration Flash chip through an SPI interface of the MCU when the analog switch chip selects the first input channel, and reading the configuration data from the configuration Flash chip through the configuration SPI interface by the FPGA so as to carry out configuration loading when the analog switch chip selects the second input channel.
  2. 2. The circuit of claim 1, wherein the SPI interface pin of the configured Flash chip comprises a chip select signal CS, a serial clock signal SCLK, a master-output-slave input signal MOSI, and a master-input-slave output signal MISO; the analog switch chip sets corresponding switching paths for the CS, SCLK, MOSI and MISO respectively to select between the first input channel and the second input channel.
  3. 3. The circuit of claim 1, wherein the serial communication interface of the MCU is a UART interface or a SCI interface; The USB-to-serial port chip is used for converting USB data of the USB interface into serial data matched with the UART interface or the SCI interface.
  4. 4. The circuit of claim 1, wherein the analog switch chip is an alternative multiplexer or a multiple analog switch device; The gating signal input end receives a GPIO control signal output by the MCU to control the selection states of the first input channel and the second input channel.
  5. 5. The circuit of claim 1, wherein the upgrade instruction comprises an enter upgrade mode instruction, write start address information, and write length information; and the MCU controls the analog switch chip to select the first input channel according to the instruction of entering the upgrade mode, and writes the configuration Flash chip according to the writing start address information and the writing length information.
  6. 6. The circuit according to claim 1, wherein the configuration Flash chip is SPI NOR Flash, and the configuration data is stored in a predetermined memory area of the configuration Flash chip.
  7. 7. The circuit of claim 6, wherein the MCU performs an erase operation on the predetermined memory area prior to writing to the configured Flash chip, the writing including page-wise writing or sector-wise writing.
  8. 8. The circuit according to claim 1, wherein the MCU reads part of data in the configuration Flash chip and performs verification after writing to the configuration Flash chip is completed, and the verification comprises verification based on a verification code and/or verification based on a cyclic redundancy check CRC.
  9. 9. The circuit of claim 1, wherein the MCU is configured to output a control signal during writing to the configuration Flash chip to place the FPGA in a reset state and/or place a configuration SPI interface of the FPGA in a state that inhibits access to the configuration Flash chip.
  10. 10. An on-line upgrading method for FPGA chip logic configuration, which is applied to the on-line upgrading circuit for FPGA chip logic configuration according to any one of claims 1 to 9, and comprises: The MCU receives configuration data and an upgrade instruction sent by an external host through the USB interface through the serial communication interface; The MCU controls the analog switch chip to select a first input channel according to the upgrading instruction, so that an SPI interface of the MCU is communicated with the configuration Flash chip; The MCU executes erasing on the configuration Flash chip through the SPI interface and writes the configuration data; The MCU controls the analog switch chip to select a second input channel, so that the configuration SPI interface of the FPGA is communicated with the configuration Flash chip, and the FPGA reads the configuration data from the configuration Flash chip through the configuration SPI interface to carry out configuration loading.

Description

FPGA chip logic configuration on-line upgrading circuit and method Technical Field The application relates to the technical field of on-line upgrading of FPGA chip logic configuration, in particular to an on-line upgrading circuit and method of FPGA chip logic configuration. Background In industrial control devices such as servo drivers, field Programmable Gate Arrays (FPGAs) are often used as core logic devices to implement high-speed timing control, interface protocol processing, and parallel computing. In order to enable the FPGA to enter the desired logic function state after the device is powered up, it is generally necessary to write logic configuration data into an external nonvolatile memory in advance, and automatically complete configuration loading by the FPGA when the device is powered up, so as to enter a user mode to start working. In the prior art, the configuration of an FPGA chip of a servo driver generally adopts the following processes that firstly, prepared hardware description language (such as VHDL) or schematic diagram describes required circuit functions, a tool is utilized to convert codes into a netlist consisting of basic logic gates such as AND gates, OR gates, NOT gates and the like and triggers, a bit stream file is generated, then a special downloader is used for connecting a USB port with a JTAG port of the FPGA, and the bit stream is burnt into an external SPI Flash of the FPGA. After the equipment is powered on again, the FPGA automatically enters a configuration flow, an internal configuration controller reads configuration data in Flash and configures an internal SRAM, and after the configuration is completed, the FPGA enters a user mode to start working. The mode is usually used for factory configuration, but when a user needs to carry out FPGA configuration upgrading in the later period, the user needs to detach the machine to open the cover and upgrade the cover through a JTAG interface in the industrial field, and the cost of manpower and material resources for batch processing is high. In addition, if the FPGA is used for writing upgrading logic and carrying out online upgrading on the configuration Flash through an external interface, the upgrading failure is easily caused once the error power failure or other blocking conditions occur in the upgrading process, and the problems that the FPGA cannot be reset and restarted, the initialization cannot pass and the like occur. Therefore, in the configuration and upgrade process of the FPGA chip of the servo driver, the field upgrade needs to be disassembled and uncapped and relies on JTAG operation, which results in high maintenance cost, and the online upgrade process is susceptible to error power down, which results in upgrade failure and difficult reset and restart, which is a problem to be solved. Disclosure of Invention The application provides an on-line upgrading circuit and method for FPGA chip logic configuration, and aims to solve the problems that in the prior art, in the FPGA chip configuration and upgrading process of a servo driver, the on-site upgrading needs to be disassembled to cover and depends on JTAG operation, so that the maintenance cost is high, the on-line upgrading process is easily affected by error power failure, the upgrading is failed, and the resetting and restarting are difficult to realize. In a first aspect, an on-line upgrade circuit for logic configuration of an FPGA chip, wherein the circuit comprises a USB interface, a USB-to-serial chip, a microcontroller MCU, an analog switch chip and a configuration Flash chip; The USB interface is connected with the USB end of the USB-to-serial port chip, and the serial port end of the USB-to-serial port chip is connected with the serial communication interface of the MCU; The analog switch chip is provided with a first input channel, a second input channel and an output channel, wherein the first input channel is connected with an SPI interface of the MCU, the second input channel is connected with a configuration SPI interface of the FPGA, and the output channel is connected with an SPI interface pin of the configuration Flash chip; the analog switch chip is also provided with a gating signal input end, and the gating signal input end is connected with the MCU; The MCU is used for receiving configuration data and an upgrade instruction sent by an external host through the USB interface through the serial communication interface, controlling the gating signal according to the upgrade instruction so as to write the configuration Flash chip through an SPI interface of the MCU when the analog switch chip selects the first input channel, and reading the configuration data from the configuration Flash chip through the configuration SPI interface by the FPGA so as to carry out configuration loading when the analog switch chip selects the second input channel. In the above scheme, optionally, the SPI interface pin of the configured Flash chip includes