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CN-122019437-A - AD acquisition system and data acquisition control method based on PCIE bus

CN122019437ACN 122019437 ACN122019437 ACN 122019437ACN-122019437-A

Abstract

The application provides an AD acquisition system and a data acquisition control method based on a PCIE bus, wherein the system comprises a multichannel AD acquisition module, a high-speed data transmission module, a PCIE bus control module and an acquisition configuration module, wherein the multichannel AD acquisition module is used for synchronously acquiring and digitally converting multichannel analog signals to acquire digital acquired data, the high-speed data transmission module is used for caching and converting the digital acquired data in a DMA mode, the PCIE bus control module is used for establishing a high-bandwidth data path between an FPGA and a CPU (central processing unit) through the PCIE bus and managing interaction of DMA transmission and control instructions, the acquisition configuration module is used for receiving configuration parameters from the CPU and dynamically configuring the multichannel AD acquisition module and the high-speed data transmission module, and the multichannel AD acquisition module, the high-speed data transmission module and the acquisition configuration module are integrated at the FPGA end and interact data and instructions with the CPU end through the PCIE bus control module. The scheme realizes the performance breakthrough of the multichannel high-speed AD acquisition system, and provides a high-reliability solution for the fields of scientific experiments and the like.

Inventors

  • ZHAO XUCHEN

Assignees

  • 天津津航计算技术研究所

Dates

Publication Date
20260512
Application Date
20251215

Claims (10)

  1. 1. An AD acquisition system based on PCIE bus, comprising: the multichannel AD acquisition module is used for synchronously acquiring and digitally converting the multipath analog signals to acquire digital acquired data; The high-speed data transmission module is used for caching and converting the digitized acquired data in a format through a DMA mode; the PCIE bus control module is used for establishing a high-bandwidth data path between the FPGA and the CPU through the PCIE bus and managing interaction between DMA transmission and control instructions; The acquisition configuration module is used for receiving configuration parameters from a CPU end and dynamically configuring the multichannel AD acquisition module and the high-speed data transmission module; The multi-channel AD acquisition module, the high-speed data transmission module and the acquisition configuration module are integrated at the FPGA end, and data and instructions are interacted with the CPU end through the PCIE bus control module.
  2. 2. The PCIE bus based AD acquisition system of claim 1, wherein the multi-channel AD acquisition module comprises: the analog front-end circuit supports multipath differential input and is integrated with a programmable gain amplifier and an overvoltage protection circuit; the high-precision ADC array consists of a plurality of ADC chips and is used for sampling multichannel input signals at a high speed in parallel; and the FPGA control logic is used for generating a low-jitter sampling clock and converting digital signals acquired by the ADC chip into AXIS bus time sequence data.
  3. 3. The PCIE bus-based AD acquisition system as recited in claim 1, wherein the high-speed data transmission module comprises: the receiving buffer FIFO is used for temporarily storing the digitized acquired data output by the multichannel AD acquisition module; the interface conversion unit is used for packaging the data in the receiving buffer FIFO into a data stream conforming to the AXIS bus time sequence; And the DMA processing unit is used for directly moving the packaged data stream to the DDR memory at the CPU end in a burst transmission mode through the PCIE bus so as to realize zero-copy transmission.
  4. 4. The PCIE bus-based AD acquisition system of claim 1, wherein the PCIE bus control module comprises: PCIE IP core, providing AXI4-STREAM and AXI4-LITE user interface, and mapping BAR0 and BAR1 address space; PIO read-write control unit, through AXI4-LITE bus and BAR0 space, receive the configuration instruction from CPU end; And the DMA read-write control unit completes high-speed data STREAM transmission from the FPGA end to the CPU end through an AXI4-STREAM bus and a BAR1 space.
  5. 5. The PCIE bus based AD acquisition system as claimed in claim 4, wherein the PCIE bus is configured by x4 Lane, the maximum link rate is not lower than 5GT/s, the BAR0 space is used for transmitting control instructions, the space size is 4KB, the BAR1 space is used for transmitting acquired data, and the space size is 2MB.
  6. 6. The AD acquisition system based on PCIE bus of claim 1 wherein the acquisition configuration module receives configuration parameters via PIO mode of PCIE bus, the parameters including ADC enable signal, sampling length, sampling repetition number and DMA transmission length.
  7. 7. A data acquisition control method based on the PCIE bus-based AD acquisition system according to any one of claims 1 to 6, characterized by comprising the steps of: the CPU end transmits acquisition parameters to an acquisition configuration module of the FPGA end through a PIO mode of the PCIE bus; The multichannel AD acquisition module at the FPGA end synchronously acquires and digitizes the multichannel analog signals according to the acquisition parameters to obtain digitized acquisition data; The high-speed data transmission module caches the digitized acquired data and converts the data into an AXIS bus data stream; The FPGA end starts DMA transmission through the PCIE bus control module, and the data stream is directly written into the DDR memory of the CPU end; the CPU side directly reads data from the DDR memory for processing.
  8. 8. The method for data acquisition control according to claim 7, wherein the step of issuing acquisition parameters includes: The CPU end configures the start and stop, sampling length, repetition number and DMA transmission length of the ADC by writing the appointed register in the PCIE BAR0 space.
  9. 9. The method for data acquisition control according to claim 7, wherein the step of starting DMA transfer comprises: the CPU terminal sets the DMA transmission length and sends out an enabling signal, and the DMA controller of the FPGA terminal immediately transmits the AXIS data stream to the DDR of the CPU terminal in a burst mode through the PCIE BAR1 space.
  10. 10. The method for data acquisition control according to claim 7, wherein the clock domain isolation and data buffering are performed on ADC acquisition data and AXIS bus time sequence through an asynchronous FIFO in a data path of an FPGA end.

Description

AD acquisition system and data acquisition control method based on PCIE bus Technical Field The application relates to the technical field of high-speed data acquisition and transmission, in particular to an AD acquisition system and a data acquisition control method based on a PCIE bus. Background In the field of high-speed data acquisition, the traditional acquisition system based on USB or Ethernet has the technical bottlenecks that (1) bandwidth is limited, USB 3.0 theoretical bandwidth is only 5Gbps, multichannel (such as 64 channels) synchronous sampling requirements (typically more than or equal to 16 GB/s) are difficult to meet, (2) high delay, protocol stack processing delay (50 mu s) causes insufficient instantaneity, microsecond-level response scenes (such as particle accelerator trigger control) cannot be met, and (3) resource occupancy rate is high, software drives frequently interrupt CPU, system load rate is higher than 40% and other tasks are influenced, and (4) expansibility is poor, firmware of the traditional acquisition card is in a solidified form, and sampling parameters cannot be dynamically adjusted. The existing traditional acquisition system design has the problems of low driving efficiency, slow interrupt response and the like, and the acquisition performance is greatly restricted. PCIE bus provides high-speed bidirectional bandwidth, supports DMA (direct memory access) -based high-speed data copy transmission, combines FPGA hardware acceleration capability, and can construct a high-throughput and low-delay acquisition system. Disclosure of Invention In view of the above-mentioned drawbacks or shortcomings in the prior art, the present application is directed to providing an AD acquisition system and a data acquisition control method based on PCIE bus; In a first aspect, the present application proposes an AD acquisition system based on a PCIE bus, including: the multichannel AD acquisition module is used for synchronously acquiring and digitally converting the multipath analog signals to acquire digital acquired data; The high-speed data transmission module is used for caching and converting the digitized acquired data in a format through a DMA mode; the PCIE bus control module is used for establishing a high-bandwidth data path between the FPGA and the CPU through the PCIE bus and managing interaction between DMA transmission and control instructions; The acquisition configuration module is used for receiving configuration parameters from a CPU end and dynamically configuring the multichannel AD acquisition module and the high-speed data transmission module; The multi-channel AD acquisition module, the high-speed data transmission module and the acquisition configuration module are integrated at the FPGA end, and data and instructions are interacted with the CPU end through the PCIE bus control module. According to the technical scheme provided by the embodiment of the application, the multichannel AD acquisition module comprises: the analog front-end circuit supports multipath differential input and is integrated with a programmable gain amplifier and an overvoltage protection circuit; the high-precision ADC array consists of a plurality of ADC chips and is used for sampling multichannel input signals at a high speed in parallel; and the FPGA control logic is used for generating a low-jitter sampling clock and converting digital signals acquired by the ADC chip into AXIS bus time sequence data. According to the technical scheme provided by the embodiment of the application, the high-speed data transmission module comprises: the receiving buffer FIFO is used for temporarily storing the digitized acquired data output by the multichannel AD acquisition module; the interface conversion unit is used for packaging the data in the receiving buffer FIFO into a data stream conforming to the AXIS bus time sequence; And the DMA processing unit is used for directly moving the packaged data stream to the DDR memory at the CPU end in a burst transmission mode through the PCIE bus so as to realize zero-copy transmission. According to the technical scheme provided by the embodiment of the application, the PCIE bus control module comprises: PCIE IP core, providing AXI4-STREAM and AXI4-LITE user interface, and mapping BAR0 and BAR1 address space; PIO read-write control unit, through AXI4-LITE bus and BAR0 space, receive the configuration instruction from CPU end; And the DMA read-write control unit completes high-speed data STREAM transmission from the FPGA end to the CPU end through an AXI4-STREAM bus and a BAR1 space. According to the technical scheme provided by the embodiment of the application, the PCIE bus is configured by adopting x4 Lane, the maximum link rate is not lower than 5GT/s, the BAR0 space is used for transmitting control instructions, the space size is 4KB, the BAR1 space is used for transmitting collected data, and the space size is 2MB. According to the technical scheme prov