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CN-122019439-A - Split-board type multi-path server system, method and device

CN122019439ACN 122019439 ACN122019439 ACN 122019439ACN-122019439-A

Abstract

The embodiment of the application provides a split-board type multipath server system, a method and a device, wherein the system comprises N main boards, an adapter board and a management board, wherein the main boards are in communication connection with each other, the main boards are respectively in communication connection with the adapter board, the adapter board is in communication connection with the management board, the main boards send in-place signals to the adapter board for representing the working states of the main boards, the adapter board sends identification signals to the main boards and the management board according to the number of in-place signals to indicate the number of the main boards in the current working states, the management board monitors and manages the main boards according to the number of the in-place signals, and a preconfigured first main board CPU starts an ultra-high speed path interconnection UPI channel corresponding to the identification signals. By applying the technical scheme of the application, the technical problems of higher hardware cost, large software complexity and inflexible mainboard layout in a multi-path server system in the prior art can be effectively solved.

Inventors

  • LU LIRONG
  • CHENG PENG
  • MENG QINGZHEN

Assignees

  • 山东至索信息科技有限公司

Dates

Publication Date
20260512
Application Date
20260128

Claims (20)

  1. 1. The system is characterized by comprising N main boards, an adapter board and a management board, wherein the main boards are in communication connection with each other, the main boards are respectively in communication connection with the adapter board, and the adapter board is in communication connection with the management board; each main board sends an in-place signal to the adapter board, wherein the in-place signal is used for representing that the current main board is in a normal working state; The adapter board sends identification signals to the main board and the management board according to the number of the received in-place signals, so that the management board monitors and manages the main boards corresponding to the identification signals, wherein the identification signals are used for representing the number of the main boards in a normal working state at present; And a first mainboard CPU in the preconfigured mainboard starts a ultra-high speed path interconnection UPI channel corresponding to the identification signal.
  2. 2. The system of claim 1, wherein the system further comprises a controller configured to control the controller, The main board comprises a CPU, a first complex programmable logic device, a plurality of first connectors and a second connector; the adapter board comprises a clock generator, N mainboard connectors, a second complex programmable logic device, a management board connector and a plurality of integrated circuit bus I2C conversion chips.
  3. 3. The system of claim 2, wherein each of said motherboards is communicatively coupled to each other via said first connector for communicating UPI signals, said motherboard is communicatively coupled to said patch panel via said second connector, and said patch panel is communicatively coupled to said management board via said management board connector.
  4. 4. The system of claim 2, wherein the motherboard further communicates with the interposer via a first signal, the first signal comprising at least one of a motherboard key signal, a motherboard clock signal, a motherboard general purpose input output signal, a motherboard I2C signal, a LTPI signal, and an enhanced serial peripheral interface ESPI signal.
  5. 5. The system of claim 4, wherein the motherboard critical signals are transmitted to other motherboards through motherboard connectors in the interposer.
  6. 6. The system of claim 4, wherein the motherboard clock signal, the motherboard general purpose input output signal, the motherboard I2C signal, the LTPI signal, and the ESPI signal are transmitted to other motherboards or the management board through the second complex programmable logic device.
  7. 7. The system of claim 2, wherein the system further comprises: The device comprises a pre-configuration module, a first main board CPU and a second main board CPU, wherein the pre-configuration module is used for configuring the CPUs in each main board through hardware configuration signals according to main board identification signals preset in the main board connector so as to determine the first main board CPU, and the main board identification signals are used for representing the positions of the main boards.
  8. 8. The system of claim 7, wherein the pre-configuration module is further configured to enable an EPSI function by the first motherboard CPU and disable the EPSI function by the remaining motherboard CPUs.
  9. 9. The system of claim 2, wherein the clock generator generates a plurality of sets of clocks that are sent to the CPU of each motherboard via the N motherboard connectors, respectively.
  10. 10. The system of claim 1, wherein the management board comprises a management board connector and a baseboard management controller.
  11. 11. The system of claim 4, wherein the system further comprises a controller configured to control the controller, The interposer also communicates with the management board via a second signal including at least one of the EPSI signal, the baseboard management controller LTPI signal, the interposer I2C signal, and the motherboard I2C signal.
  12. 12. The system of claim 1, wherein the management board is further configured to enable the I2C channel corresponding to the identification signal to monitor and manage each motherboard.
  13. 13. The system of claim 1, wherein the management board is further configured to monitor and manage the patch panel through an I2C channel between the management board and the patch panel.
  14. 14. The system of claim 1, wherein the first motherboard CPU is in handshake communication with a baseboard management controller of a management board via an EPSI bus to complete a boot process.
  15. 15. The system of claim 2, wherein a LTPI module is provided in the second complex programmable logic device, and the LTPI module is configured to coordinate power-up timing between the motherboards.
  16. 16. A method of communicating a split-board multipath server system, the method being performed by the split-board multipath server system of any of claims 1 to 15, the method comprising: acquiring an on-site signal, wherein the on-site signal is used for representing that the current main board is in a normal working state; generating identification signals according to the number of the in-place signals, wherein the identification signals are used for representing the number of the mainboards in a normal working state at present; And opening a corresponding UPI channel according to the identification signal and monitoring and managing a mainboard corresponding to the identification signal.
  17. 17. The method as recited in claim 16, further comprising: and configuring the CPU of each mainboard through a hardware configuration signal according to a preset mainboard identification signal, wherein the mainboard identification signal is used for representing the position of the mainboard.
  18. 18. The method as recited in claim 16, further comprising: And (5) coordinating the power-on time sequence among the mainboards.
  19. 19. A communications device for a split-board multipath server system, comprising: the signal acquisition module is used for acquiring an in-place signal, wherein the in-place signal is used for representing that the current main board is in a normal working state; The signal generation module is used for generating identification signals according to the number of the in-place signals, and the identification signals are used for representing the number of the main boards in a normal working state at present; and the monitoring module is used for opening the corresponding UPI channel according to the identification signal and monitoring and managing the mainboard corresponding to the identification signal.
  20. 20. The apparatus as recited in claim 19, further comprising: The CPU configuration module is used for configuring the CPU of each mainboard through a hardware configuration signal according to a preset mainboard identification signal, wherein the mainboard identification signal is used for representing the position of the mainboard.

Description

Split-board type multi-path server system, method and device Technical Field The embodiment of the application relates to the technical field of server architecture, in particular to a system, a method and a device for a split-board type multipath server. Background With the development of servers, clients have increasingly high requirements for key applications such as high-performance computing and memory computing, and for supporting the design, each large server manufacturer designs a multi-path server system based on each platform. The current main system architecture of the multi-path server is a 2-path server configuration or a 4-path server, the 2-path server or the 4-path server uses independent mainboards, and a BMC (Baseboard Management Controller, a baseboard management controller), a CPLD (Complex Programmable Logic Device, a complex programmable logic device) and the like are integrated on each mainboard, and the design mode can meet the performance requirement of the multi-path server system to a certain extent, but brings significant problems at the same time, and is as follows: 1. the hardware cost is high because each motherboard needs to be equipped with a dedicated management controller and programmable logic device, which results in an increase in hardware cost. 2. When the server system is formed by a plurality of mainboards, if the BMC on each mainboard needs to participate in the management of the whole server, a complex software mechanism is needed to coordinate the work of each BMC, so that the occurrence of conflict events is avoided, and the difficulty of software development and maintenance is further increased. 3. The motherboard layout flexibility is poor, the design of traditional 2-way or 4-way server motherboard is usually fixed, which means that different number of CPU configurations require different PCB layouts, thus limiting the layout flexibility and space utilization efficiency of the motherboard. For example, 2-way and 4-way motherboards cannot share the same PCB, resulting in a lack of flexibility in the layout inside the server. 4. The maintainability is low, the design of a plurality of independent mainboards makes it difficult to quickly locate the problem mainboards when the server fails, and the complexity and the time cost of maintenance work are increased. Disclosure of Invention The embodiment of the application provides a system, a method and a device for a division-plate type multi-path server, which are used for at least solving the problems of the system architecture of the current multi-path server in the related technology. According to one embodiment of the application, a split-board type multi-path server system is provided, which comprises N main boards, an adapter board and a management board, wherein the main boards are in communication connection with each other, the main boards are respectively in communication connection with the adapter board, and the adapter board is in communication connection with the management board; each main board sends an in-place signal to the adapter board, wherein the in-place signal is used for representing that the current main board is in a normal working state; The adapter board sends identification signals to the main board and the management board according to the number of the received in-place signals, so that the management board monitors and manages the main boards corresponding to the identification signals, wherein the identification signals are used for representing the number of the main boards in a normal working state at present; And a first mainboard CPU in the preconfigured mainboard starts a ultra-high speed path interconnection UPI channel corresponding to the identification signal. In one exemplary embodiment, the motherboard includes a CPU, a first complex programmable logic device, a plurality of first connectors, and a second connector; the adapter board comprises a clock generator, N mainboard connectors, a second complex programmable logic device, a management board connector and a plurality of integrated circuit bus I2C conversion chips. In an exemplary embodiment, the main boards are in communication connection with each other through the first connector to transmit UPI signals, the main boards are in communication connection with the adapter board through the second connector, and the adapter board is in communication connection with the management board through the management board connector. In one exemplary embodiment, the motherboard further communicates with the interposer via a first signal including at least one of a motherboard key signal, a motherboard clock signal, a motherboard general purpose input output signal, a motherboard I2C signal, a LTPI signal, and an enhanced serial peripheral interface ESPI signal. In one exemplary embodiment, the motherboard critical signals are transmitted to other motherboards through motherboard connectors in the interposer. In one exemplary em