CN-122019445-A - Method and device for training parallel interfaces of receiving side

Abstract

The application relates to the technical field of digital signal processing and provides a method and a device for training a parallel interface of a receiving side. The method includes performing a first calibration to achieve a match between a differential read enable signal received at a physical interface of a memory and a differential data strobe signal, and performing a second calibration to introduce a delay compensation after the first calibration is completed to compensate for a delay offset between the differential read enable signal and the differential data strobe signal from the physical interface to a data sampling module of a physical layer of the memory. Therefore, the deviation generated inside the physical layer is compensated, the influence of factors such as path difference, signal-to-noise ratio, working voltage, process corner voltage temperature change, signal integrity and the like is reduced, the sampling accuracy of a data sampling module inside the physical layer is improved, and the data transmission performance of the parallel interface is improved.

Inventors

• WANG JIN

Assignees

• 芯耀辉半导体科技(上海)有限公司

Dates

Publication Date

20260512

Application Date

20260414

Claims (20)

1. 1. A method for receive-side parallel interface training, the method comprising: Performing a first calibration for achieving a match between a differential read enable signal and a differential data strobe signal received at a physical interface of a memory, wherein the differential read enable signal comprises a T-phase read enable signal and a C-phase read enable signal, and the differential data strobe signal comprises a T-phase data strobe signal and a C-phase data strobe signal; performing a second calibration for introducing a delay compensation after completion of said first calibration, thereby compensating for a delay offset between said differential read enable signal and said differential data strobe signal from said physical interface to a data sampling module of a physical layer of said memory, The data sampling module is used for sampling a plurality of data signals received by the physical interface to obtain a data sampling result, wherein the T-phase reading enabling signal is used for gating the T-phase data gating signal to obtain a gated T-phase data gating signal, the C-phase reading enabling signal is used for gating the C-phase data gating signal to obtain a gated C-phase data gating signal, and the gated T-phase data gating signal and the gated C-phase data gating signal are used for the data sampling module to sample the plurality of data signals received by the physical interface to obtain a data sampling result.
2. 2. The method of claim 1, wherein the second calibration is based on a fixed bias compensation that is determined based on an evaluation of a severity of systematic bias of the memory, the evaluation being determined based on at least path differences, signal-to-noise ratio, operating voltage, process corner voltage temperature variation, and signal integrity.
3. 3. The method of claim 2, further comprising monitoring and processing, by at least one computer, the effects of the operating voltage and the process corner voltage temperature variations based on a machine learning model to determine the fixed offset compensation.
4. 4. The method of claim 1, wherein the second calibration is to introduce the delay compensation based on a dynamic bias compensation determined based on an initial delay value of the T-phase read enable signal and an initial delay value of the C-phase read enable signal, wherein the initial delay value of the T-phase read enable signal and the initial delay value of the C-phase read enable signal are determined by the first calibration.
5. 5. The method of claim 4, wherein performing the first calibration includes configuring the memory to read a preamble pattern, and then adjusting the T-phase read enable signal to match a preamble followed by a first rising edge of the T-phase data strobe signal to determine an initial delay value of the T-phase read enable signal, and adjusting the C-phase read enable signal to match a preamble followed by a first rising edge of the C-phase data strobe signal to determine an initial delay value of the C-phase read enable signal, respectively.
6. 6. The method of claim 4, wherein the second calibration determines a dynamic delay value of the T-phase read enable signal and a dynamic delay value of the C-phase read enable signal, comprising: determining a plurality of first delay values of the T-phase read enable signal according to a first step size and an adjustment range by using the initial delay value of the T-phase read enable signal as a starting point, and determining a plurality of second delay values of the T-phase read enable signal according to a second step size and the adjustment range by using the initial delay value of the T-phase read enable signal as a starting point, wherein the first step size is N times the second step size, and N is a positive integer greater than 1; Determining a plurality of first delay values of the C-phase read enable signal according to the first step size and the adjustment range using the initial delay value of the C-phase read enable signal as a starting point, and determining a plurality of second delay values of the C-phase read enable signal according to the second step size and the adjustment range using the initial delay value of the C-phase read enable signal as a starting point; Based on the combination of the first delay values of the C-phase read enable signal and the second delay values of the T-phase read enable signal, respectively adjusting the differential read enable signal so as to gate the differential data strobe signal so as to sample the data signals, obtaining an eye diagram scanning result of the T-phase read enable signal, wherein the eye diagram scanning result of the T-phase read enable signal is used for calculating an eye center position of the T-phase read enable signal, and the eye center position of the T-phase read enable signal is used for determining a dynamic delay value of the T-phase read enable signal; Based on the combination of the first delay values of the T-phase read enable signal and the second delay values of the C-phase read enable signal, respectively adjusting the differential read enable signal so as to gate the differential data strobe signal so as to sample the data signals, thereby obtaining an eye diagram scanning result of the C-phase read enable signal, wherein the eye diagram scanning result of the C-phase read enable signal is used for calculating an eye center position of the C-phase read enable signal, and the eye center position of the C-phase read enable signal is used for determining a dynamic delay value of the C-phase read enable signal.
7. 7. The method of claim 6, wherein the combining of the plurality of first delay values of the C-phase read enable signal with the plurality of second delay values of the T-phase read enable signal and the combining of the plurality of first delay values of the T-phase read enable signal with the plurality of second delay values of the C-phase read enable signal are performed by a look-up table operation, an encoding operation, or an assignment operation.
8. 8. The method of claim 6, wherein the second calibration determines a dynamic delay value of the T-phase read enable signal and a dynamic delay value of the C-phase read enable signal, further comprising: Based on the combination of the first delay values of the C-phase read enable signal and the second delay values of the T-phase read enable signal, respectively adjusting the differential read enable signal so as to gate the differential data strobe signal to sample the data signals, and filtering out the sampling result that any one of the data signals has no eye pattern, so as to obtain the eye pattern scanning result of the T-phase read enable signal; Based on the combination of the first delay values of the T-phase read enable signal and the second delay values of the C-phase read enable signal, respectively adjusting the differential read enable signal to gate the differential data strobe signal so as to sample the plurality of data signals, and filtering out the sampling result that any one of the plurality of data signals has no eye pattern, thereby obtaining the eye pattern scanning result of the C-phase read enable signal.
9. 9. The method of claim 6, wherein the first step size is one-M times a unit time interval, the adjustment range is from S times the second step size that is negative to S times the second step size that is positive, and both M and S are positive integers greater than 1.
10. 10. The method of claim 6, wherein the adjustment range is determined based on an evaluation of the severity of systematic deviation of the memory, the evaluation being determined based on at least path differences, signal-to-noise ratio, operating voltage, process corner voltage temperature variation, and signal integrity.
11. 11. The method of claim 10, further comprising monitoring and processing, by at least one computer, the effects of the operating voltage and the process corner voltage temperature variation based on a machine learning model to determine the adjustment range.
12. 12. The method of claim 4, wherein the second calibration determines the dynamic delay value of the T-phase read enable signal and the dynamic delay value of the C-phase read enable signal by a nested loop algorithm comprising: Determining a plurality of first delay values of the C-phase read enable signal according to a first step size and an adjustment range by using the initial delay value of the C-phase read enable signal as a starting point, and determining a plurality of second delay values of the T-phase read enable signal according to a second step size and the adjustment range by using the initial delay value of the T-phase read enable signal as a starting point, wherein the first step size is N times the second step size, and N is a positive integer greater than 1; Based on the combination of the plurality of first delay values of the C-phase read enable signal and the plurality of second delay values of the T-phase read enable signal, respectively adjusting the differential read enable signal to gate the differential data strobe signal so as to sample the plurality of data signals, and filtering out the sampling result that any one of the plurality of data signals has no eye pattern, obtaining an eye pattern scanning result of the T-phase read enable signal, wherein the eye pattern scanning result of the T-phase read enable signal is used for calculating the eye center position of the T-phase read enable signal, and the eye center position of the T-phase read enable signal is used for determining the dynamic delay value of the T-phase read enable signal.
13. 13. The method of claim 12, wherein the nested loop algorithm further comprises: Determining a plurality of first delay values of the T-phase read enable signal according to the first step size and the adjustment range using the initial delay value of the T-phase read enable signal as a starting point, and determining a plurality of second delay values of the C-phase read enable signal according to the second step size and the adjustment range using the initial delay value of the C-phase read enable signal as a starting point; Based on the combination of the plurality of first delay values of the T-phase read enable signal and the plurality of second delay values of the C-phase read enable signal, the differential read enable signal is respectively adjusted to gate the differential data strobe signal so as to sample the plurality of data signals, and the sampling result that any one of the plurality of data signals has no eye pattern is filtered out to obtain an eye pattern scanning result of the C-phase read enable signal, the eye pattern scanning result of the C-phase read enable signal is used for calculating an eye center position of the C-phase read enable signal, and the eye center position of the C-phase read enable signal is used for determining a dynamic delay value of the C-phase read enable signal.
14. 14. The method of claim 4, wherein the second calibration determines a dynamic delay value of the T-phase read enable signal and a dynamic delay value of the C-phase read enable signal, comprising: Using the initial delay value of the C-phase read enable signal and the initial delay value of the T-phase read enable signal as initial states of the differential read enable signals, gradually adjusting the C-phase read enable signal according to a first step size until at least one data signal is indicated to have no eye pattern in sampling results of the plurality of data signals, thereby determining an adjustment range associated with the T-phase read enable signal; Determining a plurality of first delay values of the C-phase read enable signal according to an adjustment range associated with the first step size and the T-phase read enable signal by using the initial delay value of the C-phase read enable signal as a starting point, and determining a plurality of second delay values of the T-phase read enable signal according to a second step size and an adjustment range associated with the T-phase read enable signal by using the initial delay value of the T-phase read enable signal as a starting point, wherein the first step size is N times the second step size and N is a positive integer greater than 1; Based on the combination of the plurality of first delay values of the C-phase read enable signal and the plurality of second delay values of the T-phase read enable signal, respectively adjusting the differential read enable signal to gate the differential data strobe signal so as to sample the plurality of data signals, and filtering out the sampling result that any one of the plurality of data signals has no eye pattern, obtaining an eye pattern scanning result of the T-phase read enable signal, wherein the eye pattern scanning result of the T-phase read enable signal is used for calculating the eye center position of the T-phase read enable signal, and the eye center position of the T-phase read enable signal is used for determining the dynamic delay value of the T-phase read enable signal.
15. 15. The method of claim 14, wherein the second calibration determines a dynamic delay value of the T-phase read enable signal and a dynamic delay value of the C-phase read enable signal, further comprising: Using the initial delay value of the C-phase read enable signal and the initial delay value of the T-phase read enable signal as initial states of the differential read enable signal, gradually adjusting the T-phase read enable signal according to the first step size until at least one data signal is indicated to have no eye pattern in the sampling results of the plurality of data signals, thereby determining an adjustment range associated with the C-phase read enable signal; Determining a plurality of first delay values of the T-phase read enable signal according to an adjustment range associated with the first step size and the C-phase read enable signal using the initial delay value of the T-phase read enable signal as a starting point, and determining a plurality of second delay values of the C-phase read enable signal according to an adjustment range associated with the second step size and the C-phase read enable signal using the initial delay value of the C-phase read enable signal as a starting point; Based on the combination of the plurality of first delay values of the T-phase read enable signal and the plurality of second delay values of the C-phase read enable signal, the differential read enable signal is respectively adjusted to gate the differential data strobe signal so as to sample the plurality of data signals, and the sampling result that any one of the plurality of data signals has no eye pattern is filtered out to obtain an eye pattern scanning result of the C-phase read enable signal, the eye pattern scanning result of the C-phase read enable signal is used for calculating an eye center position of the C-phase read enable signal, and the eye center position of the C-phase read enable signal is used for determining a dynamic delay value of the C-phase read enable signal.
16. 16. The method of claim 1, wherein the memory is DDR4, DDR5, or HBM.
17. 17. An apparatus for receive side parallel interface training, the apparatus comprising a calibration module for performing a second calibration for introducing a delay compensation after completion of the first calibration, thereby compensating for a delay offset between a differential read enable signal and a differential data strobe signal from a physical interface of a memory to a data sampling module of a physical layer of the memory, Wherein the first calibration is to achieve a match between the differential read enable signal and the differential data strobe signal received at a physical interface of the memory, the differential read enable signal including a T-phase read enable signal and a C-phase read enable signal, the differential data strobe signal including a T-phase data strobe signal and a C-phase data strobe signal, The T-phase reading enabling signal is used for gating the T-phase data gating signal to obtain a gated T-phase data gating signal, the C-phase reading enabling signal is used for gating the C-phase data gating signal to obtain a gated C-phase data gating signal, and the gated T-phase data gating signal and the gated C-phase data gating signal are used for the data sampling module to sample a plurality of data signals received by the physical interface to obtain a data sampling result.
18. 18. The apparatus of claim 17, wherein the apparatus is communicatively connected to the memory or the apparatus is integrated into a physical layer of the memory.
19. 19. The apparatus of claim 17, wherein the second calibration is to introduce the delay compensation based on a dynamic bias compensation determined based on an initial delay value of the T-phase read enable signal and an initial delay value of the C-phase read enable signal, wherein the initial delay value of the T-phase read enable signal and the initial delay value of the C-phase read enable signal are determined by the first calibration.
20. 20. The apparatus of claim 19, further comprising an eye scan module, the calibration module to perform the second calibration with the eye scan module to determine a dynamic delay value of the T-phase read enable signal and a dynamic delay value of the C-phase read enable signal, comprising: determining a plurality of first delay values of the T-phase read enable signal according to a first step size and an adjustment range by using the initial delay value of the T-phase read enable signal as a starting point, and determining a plurality of second delay values of the T-phase read enable signal according to a second step size and the adjustment range by using the initial delay value of the T-phase read enable signal as a starting point, wherein the first step size is N times the second step size, and N is a positive integer greater than 1; Determining a plurality of first delay values of the C-phase read enable signal according to the first step size and the adjustment range using the initial delay value of the C-phase read enable signal as a starting point, and determining a plurality of second delay values of the C-phase read enable signal according to the second step size and the adjustment range using the initial delay value of the C-phase read enable signal as a starting point; Based on the combination of the first delay values of the C-phase read enable signal and the second delay values of the T-phase read enable signal, respectively adjusting the differential read enable signal so as to gate the differential data strobe signal so as to sample the data signals, obtaining an eye diagram scanning result of the T-phase read enable signal, wherein the eye diagram scanning result of the T-phase read enable signal is used for calculating an eye center position of the T-phase read enable signal, and the eye center position of the T-phase read enable signal is used for determining a dynamic delay value of the T-phase read enable signal; Based on the combination of the first delay values of the T-phase read enable signal and the second delay values of the C-phase read enable signal, respectively adjusting the differential read enable signal so as to gate the differential data strobe signal so as to sample the data signals, thereby obtaining an eye diagram scanning result of the C-phase read enable signal, wherein the eye diagram scanning result of the C-phase read enable signal is used for calculating an eye center position of the C-phase read enable signal, and the eye center position of the C-phase read enable signal is used for determining a dynamic delay value of the C-phase read enable signal.

Description

Method and device for training parallel interfaces of receiving side Technical Field The present application relates to the field of digital signal processing technologies, and in particular, to a method and an apparatus for training a parallel interface on a receiving side. Background With the development of artificial intelligence large models and data centers, high performance memories with parallel interfaces, such as fourth generation double data rate synchronous dynamic random access memory (DDR 4 SDRAM), fifth generation double data rate synchronous dynamic random access memory (DDR 5 SDRAM), and high bandwidth memories (High Bandwidth Memory, HBM) are widely used. These memories generally support the double data rate memory physical layer interface (DDR PHY INTERFACE, DFI) protocol version 5.1, also known as DFI 5.1. To address the high-speed interconnection between a controller and a storage device, the associated protocol specification provides a parallel interfacing solution and a series of training. Prior art training schemes utilize, for example, probes or external testers to accurately determine the timing relationship between different signals and provide corresponding delay compensation, only for phase matching between signals at pins of a memory device. However, even if phase matching is performed at pins of the memory device or at the physical interface, for example, where the correct rising edge is collected, when data sampling is performed from the physical interface to the inside of the physical layer, there may still be a deviation in the phase relationship between the sampled signal and the sampled signal, and the reason why such deviation may occur is various, for example, affected by factors such as path difference, signal-to-noise ratio, operating Voltage (VDD), process corner voltage temperature variation (Process Voltage Temperature, PVT), and signal integrity. Because of the deviation generated inside the physical layer, the probe or the external tester cannot be used for accurate detection, and with the increase of the frequency and the speed of high-speed data communication, the deviation generated inside the physical layer also affects the accuracy of the final data sampling result, thereby becoming the performance bottleneck of the parallel interface. Therefore, the application provides a method and a device for training a parallel interface of a receiving side, which are used for solving the technical problems in the prior art. Disclosure of Invention In a first aspect, the present application provides a method for receiver-side parallel interface training. The method comprises the steps of executing first calibration for realizing matching between a differential read enable signal and a differential data strobe signal received by a physical interface of a memory, wherein the differential read enable signal comprises a T-phase read enable signal and a C-phase read enable signal, the differential data strobe signal comprises a T-phase data strobe signal and a C-phase data strobe signal, executing second calibration for introducing delay compensation after the first calibration is completed so as to compensate delay deviation between the differential read enable signal and the differential data strobe signal, and the data sampling module is connected from the physical interface to a physical layer of the memory, wherein the T-phase read enable signal is used for gating the T-phase data strobe signal to obtain a post-gating T-phase data strobe signal, the C-phase read enable signal is used for gating the C-phase data strobe signal to obtain a post-gating C-phase data strobe signal, and the post-gating T-phase data strobe signal is used for the plurality of sampling result obtained by the physical interface of the data sampling module. According to the application, the deviation generated inside the physical layer is compensated, so that the influence of factors such as path difference, signal-to-noise ratio, working voltage, process corner voltage temperature change, signal integrity and the like is reduced, the sampling accuracy of the data sampling module inside the physical layer is improved, and the data transmission performance of the parallel interface is improved. In a possible implementation form of the first aspect of the application, the second calibration is to introduce the delay compensation based on a fixed bias compensation, the fixed bias compensation being determined based on an evaluation result of the severity of the systematic bias of the memory, the evaluation result being determined based at least on path differences, signal-to-noise ratio, operating voltage, process corner voltage temperature variation and signal integrity. In a possible implementation manner of the first aspect of the present application, the method further includes monitoring and processing, by at least one computer, an effect of the operating voltage and the process corner voltage tem