CN-122019449-A - System for link management between multiple communication chips

Abstract

A system for link management between a plurality of communication chips is disclosed. Embodiments relate to an integrated circuit of an electronic device that coordinates activities with another integrated circuit of the electronic device. The integrated circuit includes an interface circuit and a processor circuit. The interface circuit communicates through a multi-drop bus connected to a plurality of electronic components. The processor circuit receives an authorization request from the integrated circuit via the interface circuit and the multi-drop bus. The received authorization request relates to authorization to perform an activity on the other integrated circuit. In response to receiving the authorization request, the processor circuit determines whether the other integrated circuit is authorized to perform the activity. In response to determining to authorize the other integrated circuit to perform the activity, the processor circuit sends an authorization signal to the other integrated circuit over a configurable direct connection authorizing the other integrated circuit to perform the activity.

Inventors

• H.D. O'Shea
• C.CHEN
• V.K. Lamamuti
• A. Pecher
• M. Saul
• B. Adler

Assignees

• 苹果公司

Dates

Publication Date

20260512

Application Date

20201208

Priority Date

20200528

Claims (20)

1. 1. A first integrated circuit, comprising: an interface circuit configured to communicate with the second integrated circuit through a communication channel in the electronic device, and The processor circuitry may be configured to control, the processor circuit is configured to: Receiving, via the communication channel, an assertion signal from the second integrated circuit that indicates that the second integrated circuit requests control of one or more resources shared between the first integrated circuit and the second integrated circuit for a period of time; releasing the one or more resources requested by the second integrated circuit in response to receiving the assertion signal, and After detecting the scheduling event, a computing operation utilizing the one or more resources is initiated.
2. 2. The first integrated circuit of claim 1, wherein to release the one or more resources, the processor circuit is further configured to perform at least one of: disabling one or more Radio Frequency (RF) paths; switching from using a first antenna to using a second antenna, and The transmit power of the first integrated circuit is modified.
3. 3. The first integrated circuit of claim 1, wherein to release the one or more resources, the processor circuit is further configured to release the one or more resources for a predetermined period of time.
4. 4. The first integrated circuit of claim 1, wherein the scheduling event comprises determining that the processor circuit has a scheduled computing operation having a scheduling priority that meets a threshold priority.
5. 5. The first integrated circuit of claim 1, wherein the processor circuit is further configured to: during the computing operation initiated by the processor circuit, receiving a request from the second integrated circuit for the one or more resources to perform another computing operation, and Providing a rejection signal to the second integrated circuit, the rejection signal indicating that the second integrated circuit is rejected for the one or more resources.
6. 6. The first integrated circuit of claim 5, wherein to provide the rejection signal, the processor circuit is further configured to: determining that the priority of the computing operation is higher than the priority of the other computing operation, and The reject signal is provided to the second integrated circuit in response to determining that the priority of the computing operation is higher than the priority of the other computing operation.
7. 7. The first integrated circuit of claim 5, wherein to provide the rejection signal, the processor circuit is further configured to provide the rejection signal to the second integrated circuit via the communication channel.
8. 8. The first integrated circuit of claim 5, wherein to provide the rejection signal, the processor circuit is further configured to provide the rejection signal to the second integrated circuit via a configurable direct connection separate from the communication channel.
9. 9. A method implemented by a first integrated circuit, comprising: Receiving, via a communication channel, an assertion signal from a second integrated circuit that indicates that the second integrated circuit requests control of one or more resources shared between the first and second integrated circuits for a period of time; releasing the one or more resources requested by the second integrated circuit in response to receiving the assertion signal, and After detecting the scheduling event, a computing operation utilizing the one or more resources is initiated.
10. 10. The method of claim 9, wherein releasing the one or more resources comprises at least one of: disabling one or more Radio Frequency (RF) paths; switching from using a first antenna to using a second antenna, and The transmit power of the first integrated circuit is modified.
11. 11. The method of claim 9, wherein releasing the one or more resources comprises releasing the one or more resources for a predetermined period of time.
12. 12. The method of claim 9, wherein the scheduling event comprises determining that a scheduled computing operation at the first integrated circuit has a scheduling priority that meets a threshold priority.
13. 13. The method of claim 9, further comprising: During the initiated computing operation, receiving a request from the second integrated circuit for the one or more resources to perform another computing operation, and Providing a rejection signal to the second integrated circuit, the rejection signal indicating that the second integrated circuit is rejected for the one or more resources.
14. 14. The method of claim 13, wherein providing the rejection signal comprises: Determining that the initiated computing operation has a higher priority than the other computing operation, and The reject signal is provided to the second integrated circuit in response to determining that the priority of the initiated computing operation is higher than the priority of the other computing operation.
15. 15. The method of claim 13, wherein providing the rejection signal comprises providing the rejection signal to the second integrated circuit via the communication channel.
16. 16. The method of claim 13, wherein providing the rejection signal comprises providing the rejection signal to the second integrated circuit via a configurable direct connection separate from the communication channel.
17. 17. A system, comprising: Communication channel, and A first integrated circuit communicatively coupled to a second integrated circuit via the communication channel, the first integrated circuit configured to: Receiving, via the communication channel, an assertion signal from the second integrated circuit that indicates that the second integrated circuit requests control of one or more resources shared between the first integrated circuit and the second integrated circuit for a period of time; releasing the one or more resources requested by the second integrated circuit in response to receiving the assertion signal, and After detecting the scheduling event, a computing operation utilizing the one or more resources is initiated.
18. 18. The system of claim 17, wherein to release the one or more resources, the first integrated circuit is further configured to perform at least one of: disabling one or more Radio Frequency (RF) paths; switching from using a first antenna to using a second antenna, and The transmit power of the first integrated circuit is modified.
19. 19. The system of claim 17, wherein to release the one or more resources, the first integrated circuit is further configured to release the one or more resources for a predetermined period of time.
20. 20. The system of claim 17, wherein the scheduling event comprises determining that the first integrated circuit has a scheduled computing operation having a scheduling priority that meets a threshold priority.

Description

System for link management between multiple communication chips The present application is a divisional application of chinese patent application based on application number 2020800915714, system for link management between multiple communication chips, and application number 2020, 12/8. Technical Field The present disclosure relates to coordinated operation of a plurality of Integrated Circuit (IC) chips in an electronic device. Background An electronic device may include multiple systems-on-a-chip (SOCs) for communicating with other devices using various communication protocols. As the size of the communication system in the electronic device becomes smaller while the functionality of the communication system increases, more SOCs are incorporated into the electronic device or more subsystems are added to each SOC. These SOCs may communicate with a host (e.g., a central processor or application processor) over a dedicated communication path (e.g., peripheral component interconnect express (PCIe)) to transmit data. As a result of integrating multiple communication systems and other subsystems into an electronic device, various problems or complications may arise. These problems or complications include collisions in resource usage, interference in shared or overlapping communication bands, mutually incompatible modes of operation, isolation between antennas, and transmit power management between various concurrently active SOCs, among others. In conventional electronic devices, such problems or complications are typically addressed by coordinating operation of the SOC, and problem situations are addressed by having the central processor coordinate operation across multiple SOCs. Disclosure of Invention Embodiments relate to an integrated circuit (e.g., a system on a chip (SOC)) of an electronic device that coordinates activities with another integrated circuit (e.g., another SOC) of the electronic device. The SOC includes an interface circuit and a processor circuit. The interface circuit communicates through a multi-drop bus (multi-drop) or point-to-point connection to one or more communication chips (e.g., SOCs) in the electronic device. The processor circuit receives, via the interface circuit and/or the multi-drop bus (or point-to-point connection), an authorization request from the other SOC seeking authorization to perform an activity on the other SOC. In response to receiving the authorization request, the processor circuit determines whether the other SOCs are authorized to perform the activity. In response to determining to authorize the other SOC to perform the activity, the processor circuit sends an authorization signal to the other SOC over the configurable direct connection authorizing the other SOC to perform the activity. Another SOC may also be authorized to perform activities on behalf of that SOC. Drawings Fig. 1 is a high-level diagram of an electronic device according to one embodiment. Fig. 2 is a block diagram illustrating components of an electronic device communicating over a multi-drop bus and a configurable direct connection, according to one embodiment. Fig. 3 is a block diagram illustrating a coexistence hub device according to an embodiment. FIG. 4 is a block diagram of a System On Chip (SOC) according to one embodiment. FIG. 5 is a block diagram of coordinating the operation of a pair of SOCs using a multi-drop bus and a configurable direct connection, according to one embodiment. FIG. 6 is an interaction diagram illustrating the operation and interaction of components in an electronic device according to one embodiment. Fig. 7 is a timing diagram illustrating coordination of components in an electronic device according to one embodiment. FIG. 8A is a block diagram of coordinating operation of a pair of SOCs for accessing resources using a multi-drop bus and a configurable direct connection, according to one embodiment. Fig. 8B is a timing diagram illustrating coordination of the components from fig. 8A according to one embodiment. FIG. 9A is a block diagram of coordinating the operation of a pair of SOCs for accessing shared (concurrent) resources using a multi-drop bus and a configurable direct connection, according to one embodiment. Fig. 9B is a timing diagram illustrating coordination of the components from fig. 9A according to one embodiment. Fig. 10 is a flow chart illustrating a process of coordinating operation between components of an electronic device in accordance with one embodiment. The accompanying description and specific examples describe various non-limiting embodiments for purposes of illustration only. Detailed Description Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. Numerous specific details are set forth in the following detailed description in order to provide a thorough understanding of the various described embodiments. However, the embodiments may be practiced without these specif