CN-122019459-A - Self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and system

CN122019459ACN 122019459 ACN122019459 ACN 122019459ACN-122019459-A

Abstract

The invention provides a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and a self-adaptive gridding dividing algorithm, DAG-based dependence modeling and safety sequence planning, and a pipelining parallel scheduling and integrated time sequence calibration mechanism, which solve the problems of resource fragmentation difficulty caused by static partition, system reliability risk caused by component dependence management deficiency, large reconstruction delay caused by a serial reconstruction mode, poor instantaneity and the like in the existing FPGA waveform dynamic reconstruction technology, remarkably improve the utilization rate of FPGA logic resources, realize the safety and controllability of the reconstruction process, greatly compress the whole reconstruction time, and ensure the processing precision after reconstruction through self-adaptive time sequence calibration. The method provides a high-efficiency hardware dynamic reconstruction solution for application scenes with extremely high requirements on real-time performance and reliability, such as software defined radio, comprehensive radio frequency systems and the like.

Inventors

LI JIAN
Zu Chaofan
ZHAO MING

Assignees

重庆华伟工业（集团）有限责任公司

Dates

Publication Date: 20260512
Application Date: 20251231

Claims (10)

1.A self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method is characterized by comprising the following steps: S1, carrying out dynamic reconstruction region division based on the resource requirement of a waveform component to be deployed and the real-time distribution state of FPGA resources to generate a grid layout scheme; s2, constructing a DAG model according to the data flow and control flow dependency relationship among waveform components, and carrying out topological sorting and critical path analysis based on the DAG model to obtain a safe reconstruction sequence; S3, according to the safety reconstruction sequence and the grid layout scheme, arranging the execution sequence of the reconstruction tasks by adopting a pipelined parallel scheduling strategy, and synchronously carrying out data communication and time sequence calibration to generate a reconstruction execution plan; And S4, loading partial reconfiguration bit streams to the corresponding dynamic reconfiguration areas through the FPGA configuration interfaces according to the reconfiguration execution plan, monitoring component state migration, and starting a rollback mechanism when abnormality occurs until all components are deployed successfully.
2. The method for dynamically reconstructing the FPGA waveform pipeline of the self-adaptive gridding of claim 1, wherein the dynamic reconstruction region division adopts a self-adaptive gridding division algorithm, dynamically adjusts the size and the shape of a grid unit according to the real-time resource requirements of each component, and maps each component to an independent grid unit; wherein the grid cell size is a minimum of 2 x 2 LUT granularity and a maximum of 8 x 8 LUT granularity; If there is a component with tight data interaction, the reconstruction region with the shortest adjacent or communication path is preferentially allocated.
3. The method for dynamically reconstructing the waveform pipeline of the adaptive gridded FPGA as recited in claim 2, wherein the adaptive meshing algorithm further comprises a greedy merging strategy: Traversing all unoccupied and physically adjacent idle grid cells in the FPGA resource layout based on the resource requirements of the current waveform component; Calculating the combined area of the adjacent idle grid units, and judging whether the combined area is larger than or equal to the minimum resource area threshold value required by the current waveform component; if the combined area meets the component resource area requirement, the idle grid units are combined into a continuous rectangular area to be distributed to the current waveform component for use, and the occupation state of the area is updated in the grid layout scheme.
4. The method for dynamically reconstructing the adaptive gridded FPGA waveform pipeline as recited in claim 1, wherein the DAG model is constructed with waveform components as nodes and data flow between components as directed edges, and wherein edge weights of the DAG model are dynamically updated according to real-time operation data, wherein the real-time operation data comprises one or more of an input rate, an output rate, a processing delay, a logic resource occupancy rate and an error rate.
5. The method for dynamically reconstructing the FPGA waveform pipeline of the self-adaptive gridding is characterized in that the topological sorting is realized according to data dependency constraints among nodes in the DAG model, a node sequence with an input degree of 0 is identified through a breadth-first search algorithm, and a basic reconstruction sequence meeting a precursor successor relationship among components is generated; And the critical path analysis is realized according to the accumulated value of node reconstruction time and edge communication overhead, the longest path in the DAG is calculated through a dynamic programming algorithm, the critical component sequence with the maximum total time consumption in the reconstruction process is determined, and the components on the critical path are scheduled preferentially to optimize the whole reconstruction time.
6. The method for dynamically reconstructing the FPGA waveform pipeline of the adaptive gridding as recited in claim 1, wherein the pipelined parallel scheduling strategy divides the reconstruction process into a plurality of independent phases, and the reconstruction tasks of different grid units are distributed to the independent phases for parallel execution; The timing calibration is based on the phase adjustment function of the clock management unit in the FPGA, so that the relative timing of the loading of configuration data is finely adjusted, or the timing synchronization among multiple modules is realized by inserting a programmable number of synchronization waiting periods.
7. The method for dynamically reconstructing the FPGA waveform pipeline of the self-adaptive gridding as recited in claim 6, wherein the time sequence calibration is realized through a least mean square self-adaptive filtering algorithm, and the parameter is dynamically adjusted according to the time sequence error monitored in real time, and the calibration formula is as follows: ; Wherein, the Is the first The timing error estimate for the next iteration, As a step factor, the convergence speed and stability are controlled, Is a mean square error performance function With respect to Is a gradient of (a).
8. The method for dynamically reconstructing the adaptive gridded FPGA waveform pipeline of claim 1, wherein said monitoring component state migration comprises: Before reconstruction, storing a register value and a memory state of a dynamic region into a special backup region through a state snapshot mechanism; After reconstitution, the component's ready signal and the validity of the output data are monitored.
9. The method for dynamically reconstructing the FPGA waveform pipeline of the adaptive gridding according to claim 8, wherein after the rollback mechanism is triggered, controlling an FPGA configuration interface to rollback the configuration of a dynamic region with an abnormality to a last known stable version, and recovering the running state of the region component by utilizing the state snapshot; wherein the anomaly includes a configuration frame check error, a component initialization timeout, or a functional output anomaly.
10. The self-adaptive gridding FPGA waveform pipeline dynamic reconstruction system is used for realizing the self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method according to any one of claims 1-9, and is characterized by comprising a resource partitioning unit, a self-adaptive grid generation module and a self-adaptive grid distribution module, wherein the resource partitioning unit comprises a resource state monitoring module and a self-adaptive grid generation module, is used for monitoring the real-time distribution state of FPGA logic resources, and operates a self-adaptive grid partitioning algorithm according to the resource requirement of a waveform component to be deployed to generate a dynamic grid layout scheme; the path planning unit comprises a DAG modeling module and a critical path analysis module, wherein the DAG modeling module and the critical path analysis module are used for constructing a DAG model according to the data flow and control flow dependency relationship among waveform components and carrying out topological sorting and critical path analysis to generate a safe reconfiguration sequence, the scheduling execution unit comprises a pipeline scheduler, a time sequence calibration module and a state monitoring module, the pipeline scheduler is used for carrying out pipelining strategy arrangement and executing reconfiguration tasks according to the safe reconfiguration sequence and the grid layout scheme, the time sequence calibration module is used for synchronously carrying out data communication and time sequence calibration in the reconfiguration process, the state monitoring module is used for monitoring component state migration when partial reconfiguration bit flows are loaded through an FPGA configuration interface and starting a rollback mechanism when the configuration management unit is abnormal, and the configuration management unit comprises a bit flow library management module and a version control module and is used for storing and managing partial reconfiguration bit flow files of multiple versions and providing correct configuration files for corresponding dynamic reconfiguration areas according to the reconfiguration execution plan.

Description

Self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and system Technical Field The invention relates to the technical field of digital signal processing, in particular to a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and system. Background With the development of communication devices to be unified and integrated, a single device needs to support multiple waveform protocols. Because domestic FPGA chips are limited in manufacturing process, logic resources are relatively precious, all requirements are difficult to meet through static deployment, and a dynamic reconstruction technology becomes a key. However, in the high real-time scenarios such as communication, how to realize reliable and efficient dynamic reconfiguration, avoiding system faults and performance degradation is a major technical challenge currently faced. The existing FPGA dynamic reconstruction technology mainly adopts a method of combining static partition with precompiled bit stream, and the system divides FPGA resources into a fixed static area and a plurality of dynamic reconfigurable areas (PRRs) with predefined sizes and shapes in the design stage. When running, the access port is internally configured, and the pre-generated partial bit stream is loaded into the designated PRR as required to realize the switching of hardware functions, but under the complex communication application scene, the prior art still has the following defects: The method comprises the steps of 1) dividing and rigidifying a reconstruction area, namely, carrying out static partition through fixing PRR boundaries in the prior art, failing to adapt to dynamic requirements of different waveform components on resources, resulting in low resource utilization rate and even causing reconstruction failure, 2) complicating state management and dependency relationship, namely, mainly relying on manual configuration for communication and state synchronization among components in the reconstruction process, increasing system fault risks and affecting reliability when data path errors or system deadlocks exist, 3) greatly delaying and spending the reconstruction process, namely, adopting a serial execution mode in the reconstruction process, leading to total delay being the sum of reconstruction time of each circuit, and reducing efficiency, and changing wiring in the reconstruction process, resulting in clock offset and affecting high-speed interface performance. Therefore, how to study and design a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and system capable of overcoming the defects is a problem which needs to be solved at present. Disclosure of Invention Aiming at the defects existing in the prior art, the invention provides a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method and a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction system, which dynamically distributes proper continuous physical areas for waveform components through a self-adaptive gridding partitioning algorithm, generates a safe reconstruction sequence by constructing a directed acyclic graph model of the component dependency relationship and analyzing a critical path, avoids state conflict, finally executes reconstruction tasks by adopting a pipelining parallel scheduling strategy, integrates a real-time sequence calibration and state monitoring rollback mechanism, ensures that the system can be quickly recovered in abnormal conditions, solves the problems of low resource utilization rate, high failure rate and low serial efficiency in the prior art, and realizes high-efficiency and reliable self-adaptive dynamic reconstruction. According to an embodiment of the invention, a self-adaptive gridding FPGA waveform pipeline dynamic reconstruction method comprises the following steps: S1, carrying out dynamic reconstruction region division based on the resource requirement of a waveform component to be deployed and the real-time distribution state of FPGA resources to generate a grid layout scheme; s2, constructing a DAG model according to the data flow and control flow dependency relationship among waveform components, and carrying out topological sorting and critical path analysis based on the DAG model to obtain a safe reconstruction sequence; S3, according to the safety reconstruction sequence and the grid layout scheme, arranging the execution sequence of the reconstruction tasks by adopting a pipelined parallel scheduling strategy, and synchronously carrying out data communication and time sequence calibration to generate a reconstruction execution plan; And S4, loading partial reconfiguration bit streams to the corresponding dynamic reconfiguration areas through the FPGA configuration interfaces according to the reconfiguration execution plan, monitoring component state migration, and starting a rollback mechanism when abnormality occurs until all components are deplo