CN-122019463-A - Analog memory integrated circuit based on magnetic tunnel junction array and calculation method

CN122019463ACN 122019463 ACN122019463 ACN 122019463ACN-122019463-A

Abstract

The invention discloses an analog calculation integrated circuit based on a magnetic tunnel junction array and a calculation method, which belong to the field of calculation integration and comprise a plurality of basic processing units (Xbrp), a Buffer, a multiplexer and an analog-to-digital converter (ADC), wherein each Xbrp core is a 1T1MTJ storage array, the resistance states of the front and the rear MTJs of the storage array correspond to positive weights and negative weights respectively, a read-write circuit and an analog calculation circuit are integrated, the analog calculation circuit converts the resistance states of selected multi-row MTJs into analog currents related to the high-low resistance state proportion of the MTJs in the row in parallel when calculating and enables the analog calculation circuit to output analog voltages representing the vector dot product calculation result, and the analog voltages are subjected to differential quantization of the difference value of the positive weight voltage and the negative weight voltage through the Buffer and the multiplexer after being gated, and the digital calculation result is directly obtained. The invention realizes the calculation of the data in the storage unit, greatly reduces the data handling and improves the energy efficiency and throughput of the neural network reasoning.

Inventors

LU JIAHAO
QING CHEN
FENG DAN
ZHANG WENBIAO
LIU DONGSHENG
TONG WEI
WU BING
ZHANG JUNYAN

Assignees

华中科技大学
中电海康集团有限公司

Dates

Publication Date: 20260512
Application Date: 20260130

Claims (10)

1. An analog memory integrated circuit based on a magnetic tunnel junction array, comprising: Row of lines An array of basic processing elements of a column, The number of buffers to be used in the system, Multiple multiplexers A plurality of analog-to-digital converters; The basic processing unit includes: Row of lines Magnetic tunnel junction array of columns A plurality of analog computation modules; in the magnetic tunnel junction array, a front side The resistance of the column magnetic tunnel junction corresponds to the positive weight, and then The resistance of the column magnetic tunnel junction corresponds to the negative weight, and the th Column magnetic tunnel junction and first The resistances of the column magnetic tunnel junctions are complementary; The analog computation modules are respectively connected with the magnetic tunnel junction array Bit lines are connected, word lines in the magnetic tunnel junction array are activated after the calculation Dimension(s) Signal vector activation, complete The analog calculation module is used for converting the calculation result of the corresponding bit line into analog voltage ; ; First, the A first basic processing unit The buffers are connected, and after the calculation is started, the selected basic processing unit outputs The analog voltage is sampled and held in its connected buffer; is a natural number of the Chinese characters, ; The multiplexer is Select 1 multiplexer, each buffer The output signals are respectively Multiple multiplexers, each two adjacent multiplexers being divided into one group to obtain Group multiplexer, the first Two multiplexers in the group are respectively used for connecting with the first Column analog voltage sum Column analog voltage (V); th Two differential input ends of the analog-digital converter are respectively connected with the first Two output ends of the group multiplexer are connected to finish the quantization of the corresponding calculation result; Wherein, the 、、 And Are all positive integers.
2. The analog store integrated circuit based on a magnetic tunnel junction array according to claim 1, wherein the analog computation module comprises an operational amplifier, a current mirror unit and a computation resistor; the negative input end of the operational amplifier is connected with the reference voltage The output end of the current mirror unit is connected with the control end of the current mirror unit; The input branch of the current mirror unit is connected with a corresponding bit line in the magnetic tunnel junction array, and the output branch of the current mirror unit is connected with one end of the calculation resistor; The two ends of the calculation resistor generate analog voltage proportional to the sum of conductance of the selected magnetic tunnel junction on the corresponding bit line 。
3. The magnetic tunnel junction array-based analog memory integrated circuit of claim 2, wherein the basic processing unit further comprises a read module and a write module; the read module is used for reading the resistance state of the magnetic tunnel junctions in the magnetic tunnel junction array and converting the resistance state into a digital signal; the write module is for performing set and reset operations on magnetic tunnel junctions in the array of magnetic tunnel junctions.
4. The analog integrated circuit of claim 3, wherein the read module comprises a digitally tunable reference resistance network, the resistance of the reference resistance network is adjustable, and for the resistance states of the same magnetic tunnel junction, the resistance of the reference resistance network is different, and the digital signals converted by the read module are different; the calculated resistance can be digitally trimmed; And the combination of the resistance value of the reference resistance network and the value of the resistance value of the calculated resistance in the reading module is determined through simulation verification, and the simulation verification process aims at maximizing the compensation magnetic tunnel junction resistance characteristic change and the CMOS device parameter deviation and minimizing the fluctuation range of the calculated gain.
5. The analog-to-memory integrated circuit of any one of claims 1-4, wherein the buffer comprises a 64-way time-division-multiplexed source follower.
6. The magnetic tunnel junction array-based analog-to-digital integrated circuit of any one of claims 1-4, wherein the analog-to-digital converter is a SAR ADC.
7. The analog-to-digital integrated circuit of any one of claims 1-4, further comprising a timing control module, wherein the timing control module is coupled to each analog computation module, the buffer, the multiplexer, and the analog-to-digital converter, and wherein the timing control module is configured to generate a control signal, the control signal comprising a computation enable signal, a sample-and-hold signal, a multiplexer address, and an analog-to-digital converter clock.
8. The magnetic tunnel junction array-based analog store circuit of claim 7 wherein the timing control module is further configured to control computation and quantization operations to be performed in a pipelined manner; The pipeline comprises starting the calculation process of the basic processing unit of the next row while the calculation result of the basic processing unit of the previous row executes the quantization operation, and sampling and holding the calculation result into a corresponding buffer.
9. The analog-to-memory integrated circuit of any one of claims 1-4, wherein the magnetic tunnel junction array is a 1T1MTJ array.
10. A method of calculating an analog memory integrated circuit based on a magnetic tunnel junction array according to any one of claims 1 to 9, comprising: setting the resistance state of the magnetic tunnel junctions in each magnetic tunnel junction array to make the magnetic tunnel junction array, the front part The resistance of the column magnetic tunnel junction corresponds to the positive weight, and then The resistance of the column magnetic tunnel junction corresponds to the negative weight, and the th Column magnetic tunnel junction and first The resistances of the column magnetic tunnel junctions are complementary; are all positive integers, the total number of the two is equal to the positive integer, ; Selecting a target basic processing unit by address signals according to Dimension(s) The signal vector activates the word line in the target basic unit, and after calculation is started, the target basic unit is connected with the word line The analog-to-digital converters acquire quantized calculation results.

Description

Analog memory integrated circuit based on magnetic tunnel junction array and calculation method Technical Field The invention belongs to the field of memory calculation integration, and particularly relates to a simulation memory calculation integration circuit based on a magnetic tunnel junction array and a calculation method. Background With the rapid development of artificial intelligence computing, in particular to deep neural network processing, the problem of memory walls of the traditional computing architecture is increasingly prominent. In von neumann system, when separation of a processor and a memory results in performing large-scale vector-matrix multiplication, frequent transportation of massive weights between the processor and the memory causes huge energy and time cost, and the improvement of energy efficiency and calculation strength is severely restricted. To address this challenge, computational integration technology has become the focus of research, with the core being the integration of computing functionality into memory cells. In the prior art, although the scheme based on SRAM is fast, the density is low and the static power consumption is large, and the scheme based on RRAM or Flash and other nonvolatile memories has limitations in reliability and durability. Magnetic Random Access Memory (MRAM) has shown great potential for its non-volatility, high endurance, and compatibility with CMOS processes. However, the existing partial memory integrated design can only realize simple boolean logic operation, or can generate huge energy consumption due to a large number of digital operations, and cannot efficiently support the core multiplication and addition operation of the neural network. While analog computation is attempted, a read-after-process architecture is often employed, in which the Magnetic Tunnel Junction (MTJ) resistance state is converted to an analog signal by a peripheral circuit and then transmitted to an independent computation module for processing. The method can not realize real in-situ calculation, introduces extra power consumption and area cost, is easy to cause precision loss in the signal transmission and conversion process, and limits the improvement of calculation parallelism and energy efficiency. Therefore, an innovative MRAM integrated scheme is urgently needed, the multiplication and addition operation with high parallelism can be completed by directly utilizing analog characteristics in a storage array, and the efficient differential quantization of positive and negative weights is realized, so that the bottleneck of data carrying is fundamentally overcome, and the urgent demands of edge intelligent equipment for high-energy efficiency and high-throughput rate calculation are met. Disclosure of Invention Aiming at the defects and improvement demands of the prior art, the invention provides an analog storage and calculation integrated circuit based on a magnetic tunnel junction array and a calculation method, and aims to directly utilize analog characteristics to finish multiplication and addition operation with high parallelism in a storage array, thereby effectively improving energy efficiency and throughput rate. To achieve the above object, according to one aspect of the present invention, there is provided an analog memory integrated circuit based on a magnetic tunnel junction array, comprising: Row of lines An array of basic processing elements of a column,The number of buffers to be used in the system,Multiple multiplexersA plurality of analog-to-digital converters; The basic processing unit includes: Row of lines Magnetic tunnel junction array of columnsAnalog computation module, magnetic tunnel junction array, front partThe resistance of the column magnetic tunnel junction corresponds to the positive weight, and thenThe resistance of the column magnetic tunnel junction corresponds to the negative weight, and the thColumn magnetic tunnel junction and firstThe resistances of the column magnetic tunnel junctions are complementary; the analog computation modules are respectively connected with the magnetic tunnel junction array Bit lines are connected, and word lines in the magnetic tunnel junction array are activated after the calculationDimension(s)Signal vector activation, completeThe analog calculation module is used for converting the calculation result of the corresponding bit line into analog voltage;; First, theA first basic processing unitThe buffers are connected, and after the calculation is started, the selected basic processing unit outputsThe analog voltage is sampled and held in its connected buffer; is a natural number of the Chinese characters, ; The multiplexer isSelect 1 multiplexer, each bufferThe output signals are respectivelyMultiple multiplexers, each two adjacent multiplexers being divided into one group to obtainGroup multiplexer, the firstTwo multiplexers in the group are respectively used for connecting with the firstColumn