CN-122019467-A - Core particle interconnection interface circuit, and core particle interface signal processing method and device

CN122019467ACN 122019467 ACN122019467 ACN 122019467ACN-122019467-A

Abstract

The invention discloses a core particle interconnection interface circuit, a core particle interface signal processing method and a device, wherein the core particle interconnection interface circuit comprises a core particle interface circuit, a data coding circuit and a data decoding circuit, the core particle interface circuit comprises a physical layer circuit, an inter-core particle adaptation layer circuit and a protocol layer circuit, the inter-core particle adaptation layer circuit is respectively connected with the physical layer circuit and the protocol layer circuit, the data coding circuit and the data decoding circuit are arranged between the protocol layer circuit and a system bus interface on chip or between the inter-core particle adaptation layer circuit and the protocol layer circuit, the data coding circuit is used for carrying out selective overturning processing on a sending signal of the core particle interface circuit, and the data decoding circuit is used for carrying out selective overturning processing on a receiving signal of the core particle interface circuit. The technical scheme of the invention can effectively reduce the power consumption of the core interface circuit and ensure the data transmission quality of the core interface circuit.

Inventors

ZOU XINGQI
DENG LIANGCE
ZHANG YALIN
YANG FAN
MA XIANTONG
WANG JIANBING
AN CHENG

Assignees

上海燧原科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260413

Claims (10)

1. The core particle interconnection interface circuit is characterized by comprising a core particle interface circuit, a data encoding circuit and a data decoding circuit; the chip interface circuit comprises a physical layer circuit, an inter-chip adaptation layer circuit and a protocol layer circuit, wherein the inter-chip adaptation layer circuit is respectively connected with the physical layer circuit and the protocol layer circuit; The data encoding circuit and the data decoding circuit are arranged between the protocol layer circuit and the system-on-chip bus interface or between the inter-chip adaptation layer circuit and the protocol layer circuit; The data encoding circuit is used for carrying out selective turning processing on the sending signals of the core particle interface circuit, and the data decoding circuit is used for carrying out selective turning processing on the receiving signals of the core particle interface circuit.
2. The circuit of claim 1, wherein the data encoding circuit comprises a register, a bitwise exclusive-or, an adder, a comparator, a data selector, and a bitwise inverter; The input end of the bit-wise exclusive OR is respectively connected with the input interface of the data coding circuit and the output end of the register, the output end of the bit-wise exclusive OR is connected with the input end of the adder, the output end of the adder is connected with the input end of the comparator, the input end of the bit-wise inverter is connected with the input interface, and the input end of the data selector is respectively connected with the input interface and the output end of the bit-wise inverter; the data coding circuit is used for acquiring a transmission signal output by the system-on-chip bus interface, determining the turnover amount corresponding to the transmission signal, and determining a flag bit corresponding to the transmission signal according to a comparison result of the turnover amount and a threshold value; The data coding circuit is also used for directly outputting the transmission signal or reversely outputting the transmission signal according to the corresponding flag bit of the transmission signal.
3. The circuit of claim 2, wherein the data decoding circuit comprises a data selector and a bit-wise inverter; the input end of the data selector is respectively connected with the input interface of the data decoding circuit and the output end of the bit-wise inverter; The data decoding circuit is used for obtaining a received signal of the granule core interface circuit, and directly outputting the received signal or reversely outputting the received signal according to the corresponding flag bit of the received signal.
4. The circuit of claim 3, wherein when the data encoding circuit and the data decoding circuit are disposed between the protocol layer circuit and the system-on-chip bus interface, The protocol layer circuit is used for carrying out protocol conversion on the zone bit corresponding to the sending signal and writing the converted zone bit into the flow control unit; The protocol layer circuit is also used for acquiring the zone bit corresponding to the received signal in the flow control unit and recovering the zone bit corresponding to the received signal.
5. A method of processing a core interface signal, applied to the data encoding circuit of any one of claims 1 to 4, the method comprising: Acquiring a transmission signal output by a system-on-chip bus interface, and performing bit exclusive OR processing on the transmission signal and a history signal in a register to obtain a turnover vector corresponding to the transmission signal; Accumulating the turnover vectors to obtain turnover quantity, and comparing the turnover quantity with a threshold value; And determining a zone bit corresponding to the sending signal according to the comparison result, and directly outputting the sending signal or reversely outputting the sending signal according to the zone bit.
6. The method according to claim 5, wherein determining a flag bit corresponding to the transmission signal according to the comparison result, and directly outputting or inverting the transmission signal according to the flag bit, comprises: If the turnover amount corresponding to the transmission signal is greater than or equal to a threshold value, determining the flag bit as a first identifier, and inverting and outputting the transmission signal according to the bit; If the turnover amount corresponding to the sending signal is smaller than a threshold value, determining the flag bit as a second identifier, and directly outputting the sending signal.
7. The method of claim 5, wherein the transmit signal comprises at least one of user data, address signals, and control signals.
8. A method of processing a core interface signal, applied to the data decoding circuit of any one of claims 1-4, the method comprising: Obtaining a receiving signal of a core grain interface circuit and a zone bit corresponding to the receiving signal; if the flag bit corresponding to the received signal is a first identifier, reversely outputting the received signal according to the bit; And if the flag bit corresponding to the received signal is the second identifier, directly outputting the received signal.
9. A core interface signal processing apparatus for use in a data encoding circuit as claimed in any one of claims 1 to 4, said apparatus comprising: The system comprises a transmission signal acquisition module, a register and a control module, wherein the transmission signal acquisition module is used for acquiring a transmission signal output by a system-on-chip bus interface, performing bitwise exclusive OR processing on the transmission signal and a history signal in the register, and obtaining a turnover vector corresponding to the transmission signal; The turnover quantity comparison module is used for accumulating the turnover vectors to obtain turnover quantity and comparing the turnover quantity with a threshold value; And the transmitting signal output module is used for determining a zone bit corresponding to the transmitting signal according to the comparison result, and directly outputting the transmitting signal or reversely outputting the transmitting signal according to the zone bit.
10. A core interface signal processing apparatus for use in a data decoding circuit as claimed in any one of claims 1 to 4, said apparatus comprising: the marker bit acquisition module is used for acquiring a receiving signal of the kernel interface circuit and a marker bit corresponding to the receiving signal; The receiving signal inverting module is used for inverting and outputting the receiving signal according to the bit if the bit of the sign corresponding to the receiving signal is the first identifier; and the received signal output module is used for directly outputting the received signal if the flag bit corresponding to the received signal is the second identifier.

Description

Core particle interconnection interface circuit, and core particle interface signal processing method and device Technical Field The present invention relates to the field of computer technologies, and in particular, to a core interconnection interface circuit, and a method and an apparatus for processing a core interface signal. Background The Die (Chiplet) technology is a new chip design method that breaks down a complex chip into multiple small functional modules (Die) and then integrates them together through advanced packaging. At present, with the increase of the rate of a core interface and the increasing demand of system bandwidth, the power consumption of a core interface circuit is higher and higher, and the generated power supply noise is also larger and higher. Therefore, it is desirable to provide an effective technical means for reducing the power consumption of the core interface circuit while ensuring the data transmission stability of the core interface circuit. Disclosure of Invention The invention provides a core particle interconnection interface circuit, a core particle interface signal processing method and a core particle interface signal processing device, which can effectively reduce the power consumption of the core particle interface circuit and ensure the data transmission quality of the core particle interface circuit. According to an aspect of the present invention, there is provided a core interconnection interface circuit including a core interface circuit, a data encoding circuit, and a data decoding circuit; the chip interface circuit comprises a physical layer circuit, an inter-chip adaptation layer circuit and a protocol layer circuit, wherein the inter-chip adaptation layer circuit is respectively connected with the physical layer circuit and the protocol layer circuit; The data encoding circuit and the data decoding circuit are arranged between the protocol layer circuit and the system-on-chip bus interface or between the inter-chip adaptation layer circuit and the protocol layer circuit; The data encoding circuit is used for carrying out selective turning processing on the sending signals of the core particle interface circuit, and the data decoding circuit is used for carrying out selective turning processing on the receiving signals of the core particle interface circuit. According to another aspect of the present invention, there is provided a method for processing a core interface signal, which is applied to the data encoding circuit according to any embodiment of the present invention, the method including: Acquiring a transmission signal output by a system-on-chip bus interface, and performing bit exclusive OR processing on the transmission signal and a history signal in a register to obtain a turnover vector corresponding to the transmission signal; Accumulating the turnover vectors to obtain turnover quantity, and comparing the turnover quantity with a threshold value; And determining a zone bit corresponding to the sending signal according to the comparison result, and directly outputting the sending signal or reversely outputting the sending signal according to the zone bit. According to another aspect of the present invention, there is provided a method for processing a core interface signal, which is applied to the data decoding circuit according to any embodiment of the present invention, the method including: Obtaining a receiving signal of a core grain interface circuit and a zone bit corresponding to the receiving signal; if the flag bit corresponding to the received signal is a first identifier, reversely outputting the received signal according to the bit; And if the flag bit corresponding to the received signal is the second identifier, directly outputting the received signal. According to another aspect of the present invention, there is provided a core interface signal processing apparatus applied to the data encoding circuit according to any one of the embodiments of the present invention, the apparatus including: The system comprises a transmission signal acquisition module, a register and a control module, wherein the transmission signal acquisition module is used for acquiring a transmission signal output by a system-on-chip bus interface, performing bitwise exclusive OR processing on the transmission signal and a history signal in the register, and obtaining a turnover vector corresponding to the transmission signal; The turnover quantity comparison module is used for accumulating the turnover vectors to obtain turnover quantity and comparing the turnover quantity with a threshold value; And the transmitting signal output module is used for determining a zone bit corresponding to the transmitting signal according to the comparison result, and directly outputting the transmitting signal or reversely outputting the transmitting signal according to the zone bit. According to another aspect of the present invention, there is provided a core interf