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CN-122019842-A - Canonical key generation method and device for DC-DC converter topology library processing

CN122019842ACN 122019842 ACN122019842 ACN 122019842ACN-122019842-A

Abstract

The invention discloses a method and a device for generating a standard key for processing a DC-DC converter topology library, which sequentially complete graph model construction, element multi-attribute coding, versioning mapping management, standard specification, standard key record generation, analysis review and structure analysis from connection relation data and port definition of a topology to be processed, realize warehousing duplication removal and stable index, structure interpretation and sub-module boundary display, and use structure similarity measurement based on a standard expression for classification or screening. The method of the invention realizes equivalent topological stability and key storage by generating a deterministic standard key as a main key of a database, wherein the standard key explicitly reserves a series-parallel hierarchy, can be analyzed into a hierarchy tree to output an interpretable structure group, calculates the structural similarity of two standard keys, forms a complete closed loop in the aspects of uniqueness, reversibility, interpretability and engineering auditability of topological expression, and supports standard storage, analysis review and structural analysis application of the topological database.

Inventors

  • JIN KE
  • LI XINGSHUO

Assignees

  • 南京师范大学

Dates

Publication Date
20260512
Application Date
20260413

Claims (10)

  1. 1. A canonical key generation method for DC-DC converter topology base processing, comprising the steps of: Step 1, obtaining topology input of a DC-DC converter to be analyzed, wherein the topology input comprises connection relation data, port definition and key function nodes, and preprocessing and consistency verification are carried out to obtain an element set, a connection point set V, a port set T and a key node set K; step 2, constructing an undirected weighted graph model, expressing the connection relation of the topological input through a graph structure, and adopting undirected edge bearing direction attributes; Step 3, coding each element, extracting type codes And direction encoding Determining port domain markers in combination with port set T Generating extended function labels Obtaining element attributes Reversible bijective coding through multiple nesting to generate unique index ; Step 4, unique index Element attributes The mapping of (2) is written into a versionable attribute dictionary, and port signatures and marking information of a key node set K are generated for each topology instance to carry out versionable mapping management; Step 5, based on the undirected weighted graph model, simplifying according to turns to obtain a unique and recheckable canonical key under the constraint of the same port set T and the key node set K; step 6, generating and outputting a standard key record comprising a standard key, a dictionary version and minimum metadata; And 7, carrying out grammar analysis and consistency rechecking on the standard keys, recovering the serial-parallel hierarchical tree, outputting the minimum conflict sub-expression, carrying out index storage by taking the standard keys as the main keys of the database in topology library application, and outputting sub-module boundaries, serial-parallel combination relations and key node and port participation conditions corresponding to brackets of each layer based on the recovered serial-parallel hierarchical tree to provide structure interpretation and similarity measurement.
  2. 2. The canonical key generation method of claim 1, wherein in step 1: The connection relation data comprises an element list, an electric node identifier net connected with each element endpoint and an element attribute field, wherein the element list, the electric node identifier net and the element attribute field are represented by a netlist, a connection matrix or an adjacent matrix; the key function nodes are obtained by user labeling or automatically generated by a system according to preset rules, and if the key function nodes do not exist, the key function nodes are empty sets; The consistency check comprises port definition integrity, node identification legality and uniqueness, existence of element endpoint reference nodes and element attribute field value falling field check.
  3. 3. The canonical key generation method according to claim 1, wherein in step 2, the undirected weighted graph model maps each connection point in the connection point set V to a graph node, and maps each electrical element to a graph edge connecting the electrical nodes at both ends thereof; the graph edge carries a weight field, and the weight field is composed of index coding values generated by reversible mapping of element attributes and is used for expressing the unique identity and attribute of the element; For elements having a direction or polarity, the direction or polarity is represented by ordered pairs of end points at both ends of the element, the ordered pairs being defined by netlist end point order or device symbol definition and encoded in the direction in canonical key generation And (5) curing.
  4. 4. The method according to claim 1, wherein in step 3, the element attribute is set By Cantor pairing function Reversible bijective coding is carried out on multiple nested parts of the code to obtain a unique index : ; Indexing the unique index The edge weights in the graph model are stored as corresponding elements for subsequent normalized merging and decoding rechecking.
  5. 5. The canonical key generation method of claim 1, characterized in that in step 5, the round-robin reduction is performed as follows: Step 5.1, each round of finding all the parts which can be connected in parallel firstly, merging by using a preset parallel connector, finding all the parts which can be connected in series again, merging by using a preset series connector, writing each object which participates in merging into a sub-expression character string with a fixed format before each merging, and writing leaf objects into indexes thereof The substructures are written as bracketed series-parallel expressions, with parallel and series connectors used within the expression, and contain indexes at the leaves ; Step 5.2, carrying out deterministic sorting on the objects participating in merging according to a canonical sorting key: Sequentially determining a sorting order according to the leaf number ascending order, the subtree height ascending order, the operator name classical order and the stable hash value ascending order if the sorting results are the same; And 5.3, repeating the processes from the step 5.1 to the step 5.2 until simplification can not be carried out, and obtaining a unique and recheckable standard key under the constraint of the same port set T and the key node set K.
  6. 6. The canonical key generation method of claim 1, wherein in step 6, the canonical key record, a field includes: canonical key, which is a key for topology library deduplication and indexing; minimum metadata required for decoding and consistency review, including unique index Mapping version number of element attribute or dictionary ID, port signature and key node reserved mark; the error location field when decoding or rechecking fails includes the failure cause, the conflict location, and the minimum conflict sub-expression.
  7. 7. The canonical key generation method of claim 1, characterized in that in step 7, the syntax parsing and consistency review is performed by: performing top-down grammar analysis on the standard key, and recovering the serial-parallel hierarchical tree according to the operator priority and the bracket structure; Index at leaf Inversely mapping the element attribute, and generating a normalized equivalent topological structure and a rechecking result by combining the port signature, the port domain mark and the key node reservation mark; For the non-pure serial-parallel connection substructure existing in the input, an interface of an unregulated subgraph and signature occupation thereof are adopted, the unregulated subgraph signature is regarded as a super element in the regulation, the follow-up regulation, regulation key generation and consistency review are participated, the original node number and all internal details are not promised to be restored, and pseudo-collision caused by the difference of input numbers is avoided.
  8. 8. The method according to claim 7, wherein in step 7, in the topology base application, the canonical key is stored as a database primary key in an index: judging whether the operation is repeated or not by using a standard key during warehousing, and performing incremental warehousing management; And when inquiring, the topology item is quickly positioned by the standard key, and a corresponding standard key record and a rechecking result are output.
  9. 9. The canonical key generation method of claim 7, wherein in step 7, the structure interpretation and similarity metrics are as follows: based on the analyzed serial-parallel hierarchical tree, outputting the sub-module boundary, serial-parallel combination relation and key node or port participation condition corresponding to each bracket layer to provide structure interpretation; Constructing subtree fingerprint vectors for grammar trees corresponding to two standard keys, namely, for each node u in the grammar tree, calculating subtree structure fingerprints with u as a root and depth not exceeding D, and generating node labels by adopting bottom-up certainty heavy labels and a fixed hash function H, wherein the method comprises the following steps: leaf node label: ; Internal node label: ; Wherein, the The fixed hash function is represented as a function of a fixed hash, Representing the identity of the leaf node, Index markers representing leaf elements corresponding to node u; A port domain label representing a corresponding element of node u; An extended function flag representing a corresponding element of node u; The operator type corresponding to the internal node u is represented, a series connector is taken when the nodes are connected in series, and a parallel connector is taken when the nodes are connected in parallel; The child nodes are child nodes of the node u, and the sequence of the child nodes is fixed according to the deterministic ordering result when the standard key is generated; Representing child nodes Is a label of (2); Collecting each node label as sub-tree fingerprints within the range of depth 1 to D, counting the occurrence times of each fingerprint, and weighting the counts according to the participation conditions of depth, port domains and key nodes to form a sparse vector X; And defining the structural similarity of the two topologies as weighted cosine similarity of the sparse vector X, backtracking the common subtree fingerprint with the largest contribution as a corresponding sub-expression, and outputting a similarity reason and a similarity sub-module.
  10. 10. A canonical key generation device for DC-DC converter topology base processing, for use in the method of any one of claims 1 to 9, comprising: the topology input and preprocessing module is used for acquiring the topology input of the DC-DC converter to be analyzed and preprocessing the topology input; the diagram construction module is used for constructing an undirected weighted diagram model and carrying out connection relation expression on the topology input through a diagram structure; The element multi-attribute reversible coding module is used for coding each element to obtain element multi-attribute, reversible bi-injection coding is carried out through multi-element nesting, and a unique index is generated; The attribute dictionary and versioning management module is used for writing the mapping of the index and the element attribute into the versionable attribute dictionary, generating port signatures and marking information of the key node set for each topology instance, and carrying out versioning mapping management; The deterministic serial-parallel protocol module is used for generating a standard key according to a rule of firstly connecting in parallel and then connecting in series and based on a standard ordering key; The canonical key record generation module is used for generating and outputting canonical key records, and comprises canonical keys, dictionary versions and minimum metadata; The canonical key analysis and consistency rechecking module is used for recovering the normalized equivalent topological structure according to the canonical key record and outputting the minimum conflict sub-expression; and the structure interpretation and similarity calculation module is used for outputting sub-module boundaries corresponding to bracket levels and calculating the structure similarity based on sub-tree fingerprint vectors.

Description

Canonical key generation method and device for DC-DC converter topology library processing Technical Field The invention relates to the field of power electronic topology modeling and computer aided analysis, in particular to a canonical key generation method and device for processing a DC-DC converter topology library. Background In recent years, a computer-aided or artificial intelligence method can generate a large number of candidate topologies of the power electronic converter in a short time, so that the construction and automatic screening of a topology library become common requirements. However, there are often a large number of equivalent topologies or topologies with highly similar structures in the candidate topologies, and if there is no effective topology specification representation and stable indexing mechanism, the redundancy in the library will be increased, the screening efficiency will be reduced, and the repeated analysis cost will be increased. According to a traditional topology analysis method based on function module decomposition, a complex converter is decomposed into a plurality of basic function units (such as buck/boost basic units and the like), the topology is understood and classified and analyzed through identification and combination of the function modules, the decomposition process depends on expert heuristic rules and lacks unified standards, when the topology is faced with large-scale candidate topology, the efficiency is low, the stability and the consistency are insufficient, and only and recheckable standard representation is difficult to form for database level duplicate removal and retrieval. The existing graph theory and computer-aided equivalent identification method, such as a loop matching (loop matching) based computer-aided equivalent identification method, converts topological structure information into loop set/matching problems, and judges whether an equivalent relationship exists or not through searching and matching, so that equivalent identification can be automatically completed to a certain extent, but the equivalent identification method depends on exhaustive or high-cost searching, and as the complexity of the topology increases, the identification efficiency decreases, and is unfavorable for large-scale processing and rapid screening of a topology library. The topology simplification/comparison method based on graph modeling converts a circuit into a graph structure, merges or simplifies the graph structure according to rules, compares or further calculates simplification results, can reduce part of structural redundancy, improves subsequent processing efficiency, but often needs to calculate algebraic expressions or structural relations which are more complex than the calculation, has more complicated engineering realization, and in addition, if a deterministic standardized output mechanism is absent, the same topology can generate different representations under different traversal or simplification sequences, which is unfavorable for stable warehouse-in indexes and duplication elimination. In order to avoid exhaustive search and improve discrimination efficiency, researches are carried out by combining graph theory and number theory, endowing prime numbers to elements and forming standardized expression, converting equivalent discrimination into graph isomorphic discrimination, and improving automation of equivalent recognition and efficiency to a certain extent. However, the generated expression often lacks direct physical structure interpretability, is difficult to provide quantifiable structural similarity, is unfavorable for further topological classification, similar retrieval ordering and element role analysis, and has insufficient space for expanding multiple attributes (such as directions, port roles and the like) of elements and an unambiguous coding mechanism in engineering application. With the development of neural network technology, research and exploration have been performed to extract circuit/topology features by using models such as a graph neural network, wherein the circuit topology is used as a graph input model, and after training, the embedded or feature is output for classification/identification, so that a strong feature expression capability can be obtained on a certain task. However, the model has certain black box property, and can bring challenges in verification, responsibility and auditability in engineering scenes, which is unfavorable for the topology library processing flow which needs rechecking, interpretation and reversible verification. In summary, the prior art is limited by applicable conditions or efficiency issues (e.g., dual/modular decomposition/exhaustive matching), or has shortcomings in uniqueness of canonical representations, expression interpretability, and reversible validation and engineering auditability. In order to meet the requirement of large-scale application of a topology library, a unif