CN-122020102-A - Circuit fragile node identification method based on static feature fusion

CN122020102ACN 122020102 ACN122020102 ACN 122020102ACN-122020102-A

Abstract

A circuit fragile node identification method based on static feature fusion. The method comprises the steps of constructing a circuit basic information base, forming a standardized feature set, constructing a weighted fusion feature matrix, constructing a fragile node identification model, determining a fragile node list and the like. The invention only relies on static information of a circuit to develop feature extraction and model training, can greatly shorten the identification period and adapt to a large-scale complex circuit, covers four static features including trigger topology, bus association, feedback loop and process attribute, fully captures the inherent attribute and association characteristic of circuit nodes, ensures data integrity through sub-module flattening and bus signal expansion, adopts an entropy objective weighting and multi-model integration strategy, can effectively improve the accuracy and generalization capability of fragile node identification, and simultaneously unifies process library analysis, netlist processing and feature calculation frameworks, can adapt to digital circuit designs of different frameworks, and can provide accurate fragile node reference for the initial stage of circuit reliability design.

Inventors

FAN YUYANG
ZHOU HAIPENG
DUAN YACHEN
ZHANG SHUSEN
Cao Jiuzhe

Assignees

中国民航大学

Dates

Publication Date: 20260512
Application Date: 20260127

Claims (6)

1. A circuit fragile node identification method based on static feature fusion is characterized by comprising the following steps in sequence: Extracting a module structure, a signal topology and device attributes, analyzing a circuit gate level netlist and a process library file, then analyzing the module structure, the signal topology, signal splitting and device attributes, completing sub-module flattening, bus signal unfolding and constant signal extraction, and constructing a circuit topology diagram, thereby constructing a circuit basic information library; Step 1), extracting multidimensional static features including trigger topology, bus association, feedback loops and process attributes by utilizing the circuit basic information base constructed in the step 0) to form a standardized feature set; Step 2), processing the standardized feature set obtained in the step 1) by adopting a min-max standardization method to eliminate dimension influence, calculating feature weights by utilizing an entropy method, and constructing a weighted fusion feature matrix; step 3), respectively training three models of a random forest and K-linear, xgboost by using the weighted fusion feature matrix constructed in the step 2), and integrating the three trained models through a weighted voting strategy, thereby constructing a fragile node identification model; and 4) inputting the weighted fusion feature matrix obtained after the processing of the steps 0) to 2) to the circuit to be identified, inputting the fragile node identification model obtained in the step 3), outputting the vulnerability score of the node, and finally determining the fragile node list according to the statistical threshold.
2. The method for identifying circuit fragile nodes based on static feature fusion according to claim 1, wherein in step 0), the method for extracting module structure, signal topology and device attribute, analyzing a circuit gate level netlist and a process library file, then analyzing module structure, signal topology, signal splitting and device attribute, completing sub-module flattening, bus signal expansion and constant signal extraction, and constructing a circuit topology graph comprises the following steps: (1) Extracting attribute information of a module, an instance, a port, a signal and a device by adopting a regular matching and recursive traversal algorithm, analyzing a circuit gate level netlist and a process library file, and establishing a multidimensional association table and a dictionary; (2) And lifting the bottom layer instance of the non-tool submodule to the top layer through recursively tracing the inner instance of the submodule to flatten the submodule, and reserving the original signal connection relation, wherein the formula is as follows: ; In the formula, In order to flatten the set of instances, The bottom instance set of the kth sub-module, m is the number of sub-modules; (3) Splitting signals including bus signals and unit width signals into transmission signals and constant signals based on a signal naming format, extracting the constant signals, associating the constant signals to corresponding ports and connecting lines, and storing the constant signals in a dictionary; (4) Based on the regular expression, the bus format is identified, independent unit width signals are split and generated according to bits, and therefore the bus signals are unfolded, and an unfolding logic formula is as follows: ; In the formula, M, N is a bus bit width boundary for the expanded bus signal set; (5) And constructing a circuit topological graph G= (V, E) representing the topological relation by taking the example port and the signal as nodes and the driving relation as a directed edge, wherein V is a node set and E is a directed edge set.
3. The method for identifying a circuit fragile node based on static feature fusion according to claim 1, wherein in step 1), the multi-dimensional static feature comprises: (1) Trigger fan-in number : ; In the formula, In order to be a trigger for the object, In the case of a further trigger which is a trigger, In order to assemble a set of logic devices, The signal driving relationship is represented by a signal, Representing the number of the set elements; (2) Trigger fanout : ; In the formula, Other triggers; (3) Total FF number affecting input : ; In the formula, For slave flip-flops To target trigger Is effective signal path of (a); (4) Total FF number affecting output : ; In the formula, To be a slave target trigger To the trigger Is effective signal path of (a); (5) Path characteristics to PI/PO ports: ; In the formula, As a result of the fact that the target node, 、 Respectively reachable PI and PO port sets, The group of formulas respectively calculate the shortest path series, average path series and longest path series from the target node to all PI/PO ports, and the shorter the path series is; (6) Bus attribution identification : ; In the formula, The node marked as 1 belongs to the bus signal; (7) Bus location : ; (8) Bus length : ; (9) Feedback loop identification : ; In the formula, A closed loop path which is the trigger itself and returns to the input after a plurality of examples from the output; (10) Feedback loop depth : ; (11) Constant drive connection number : ; In the formula, A set of constant signals identified for step 0); Is the effective path from constant signal c to target node n i ; (12) Drive strength : ; In the formula, Is a device in a process library Is used for driving the intensity parameter of the motor.
4. The method for identifying circuit fragile nodes based on static feature fusion according to claim 1, wherein in the step 2), the method for processing the standardized feature set obtained in the step 1) by using a min-max standardization method to eliminate dimension influence, then calculating feature weights by using an entropy method, and constructing a weighted fusion feature matrix is as follows: (1) Performing min-max standardization on the original characteristic values in the standardized characteristic set obtained in the step 1): ; In the formula, The jth original eigenvalue of the ith node, The characteristic value is normalized, and n is the total number of nodes; (2) Based on the normalized characteristic values, calculating characteristic weights by using an entropy method: ① Calculating the specific gravity of the ith node under the jth normalized characteristic value: ; ② Based on the above specific gravity, the entropy value of the j-th feature is calculated: ; ③ Based on the entropy values, the weight of the j-th feature is calculated: ; wherein m is the total number of features, satisfying ; (3) Based on the normalized eigenvalues and weights, a weighted fusion eigenvector is constructed: 。
5. The method for identifying the fragile node of the circuit based on the static feature fusion according to claim 1, wherein in the step 3), the weighted fusion feature matrix constructed in the step 2) is used for respectively training three models of a random forest and K-linear, xgboost, and the three trained models are integrated through a weighted voting strategy, so that the method for constructing the fragile node identification model is as follows: (1) Dividing the weighted fusion feature matrix into a training set, a verification set and a test set according to the proportion of 7:1.5:1.5; (2) Training a single model, namely respectively training, verifying and testing the following three models by using the training set, the verification set and the test set to obtain output scores, wherein the physical meaning of the output scores is error contribution rate, expressed in percentage form, and is 100% at maximum: ① Random forest based on multiple decision tree integration and with Gini coefficient as splitting criterion; ② K-linear, namely, a linear model with regularization, and minimizing a square loss function; ③ Xgboost gradient lifting tree model, through residual iterative optimization; (3) The weighted voting integration is used for constructing a fragile node identification model, wherein model weights are distributed according to the accuracy of a verification set, the vulnerability score of the node is calculated, and the formula is as follows: ; In the formula, The vulnerability score for the ith node, The output of the kth model is scored, Is the model weight, satisfies And model weight Positively correlated to the accuracy of the model validation set.
6. The method for identifying the fragile nodes of the circuit based on the static feature fusion according to claim 1, wherein in the step 4), the method for finally determining the list of the fragile nodes according to the statistical threshold value comprises the following steps of: (1) And calculating a statistical threshold value, namely determining the statistical threshold value based on the average value and the standard deviation of the vulnerability scores of all the nodes, wherein the formula is as follows: ; In the formula, As a mean value of the vulnerability score, Is the standard deviation of the score; (2) Vulnerable node determination when node vulnerability score And then ordering all the fragile nodes according to the vulnerability score from high to low to form a fragile node list, wherein the formula is as follows: ; In the formula, Is a set of fragile nodes; The higher the vulnerability score, the stronger the vulnerability.

Description

Circuit fragile node identification method based on static feature fusion Technical Field The invention belongs to the technical field of integrated circuit design and fault diagnosis, and particularly relates to a circuit fragile node identification method based on static feature fusion, which is suitable for vulnerability assessment and fault injection optimization of a gate level circuit in an EDA (electronic design automation) process. Background Along with the continuous shrinking of integrated circuit process nodes, the complexity of the circuit grows exponentially, and the conventional fragile node identification method relying on gate level simulation and fault injection faces the problems of low efficiency and incomplete coverage. In the prior art, fragile node identification is dependent on dynamic time sequence simulation, a large amount of calculation resources and time are required to be consumed, comprehensive extraction of static structural features and comprehensive performance features of a circuit is difficult to achieve, and meanwhile, the existing feature extraction tool lacks a unified process library analysis, netlist processing and feature calculation framework, has the defects of single feature dimension, incomplete bus signal expansion, inaccurate feedback loop identification and the like, and therefore the recognition accuracy of subsequent machine learning model training is limited. In addition, in the conventional method, the flip-flop (FF) is used as a core component of the circuit sequential logic, and the static structural features (such as fan-in fan-out and PI/PO connection relations), bus attributes, feedback loops and other key information are not integrated by the system, so that it is difficult to form a multi-dimensional feature data set to support accurate identification of fragile nodes. Therefore, a high-efficiency and comprehensive static feature extraction method is needed, a unified analysis-modeling-feature extraction framework is constructed, and quick and accurate circuit fragile node identification is realized by combining machine learning. Disclosure of Invention In order to solve the problems, the invention aims to provide a circuit fragile node identification method based on static feature fusion. In order to achieve the above purpose, the method for identifying the circuit fragile node based on static feature fusion provided by the invention comprises the following steps in sequence: Extracting a module structure, a signal topology and device attributes, analyzing a circuit gate level netlist and a process library file, then analyzing the module structure, the signal topology, signal splitting and device attributes, completing sub-module flattening, bus signal unfolding and constant signal extraction, and constructing a circuit topology diagram, thereby constructing a circuit basic information library; Step 1), extracting multidimensional static features including trigger topology, bus association, feedback loops and process attributes by utilizing the circuit basic information base constructed in the step 0) to form a standardized feature set; Step 2), processing the standardized feature set obtained in the step 1) by adopting a min-max standardization method to eliminate dimension influence, calculating feature weights by utilizing an entropy method, and constructing a weighted fusion feature matrix; step 3), respectively training three models of a random forest and K-linear, xgboost by using the weighted fusion feature matrix constructed in the step 2), and integrating the three trained models through a weighted voting strategy, thereby constructing a fragile node identification model; and 4) inputting the weighted fusion feature matrix obtained after the processing of the steps 0) to 2) to the circuit to be identified, inputting the fragile node identification model obtained in the step 3), outputting the vulnerability score of the node, and finally determining the fragile node list according to the statistical threshold. In step 0), the module structure, the signal topology and the device attribute are extracted, the circuit gate level netlist and the process library file are analyzed, then the module structure, the signal topology, the signal splitting and the device attribute are analyzed, the sub-module flattening, the bus signal unfolding and the constant signal extraction are completed, and the method for constructing the circuit topology graph is as follows: (1) Extracting attribute information of a module, an instance, a port, a signal and a device by adopting a regular matching and recursive traversal algorithm, analyzing a circuit gate level netlist and a process library file, and establishing a multidimensional association table and a dictionary; (2) And lifting the bottom layer instance of the non-tool submodule to the top layer through recursively tracing the inner instance of the submodule to flatten the submodule, and reserving the origi