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CN-122020193-A - Waveform recognition implementation method for waveform template matching based on FPGA

CN122020193ACN 122020193 ACN122020193 ACN 122020193ACN-122020193-A

Abstract

The application discloses a waveform recognition implementation method based on FPGA (field programmable gate array) waveform template matching, which adopts a flexible template configuration mechanism to support custom waveform recognition without relying on deep learning and large-scale data training, and simultaneously adapts to different precision, frequency range and direct current bias scenes through a configurable frequency parameter and dynamic zero calibration mechanism. In the hardware implementation level, the parallel and pipeline characteristics of the FPGA are fully exerted, an n-path parallel processing architecture is constructed, a preferred lightweight result processing strategy from intra-group iterative update to inter-path is matched, the occupation of storage resources is obviously reduced, and the recognition speed and reliability are ensured through a dual-mode decision mechanism of quick matching and full matching. The method solves the defects of the traditional template matching method, simultaneously avoids the problems of difficult deployment, high calculation force requirement and strong data dependence of the deep learning scheme, and remarkably improves the practical value of the system under multiple scenes.

Inventors

  • LI XIAOYONG
  • WANG XING
  • Ju Feixiang
  • LIU LEI
  • DU RONGZHEN
  • BAI XUERU
  • ZHOU FENG

Assignees

  • 西安电子科技大学

Dates

Publication Date
20260512
Application Date
20260112

Claims (10)

  1. 1. The waveform recognition implementation method based on the FPGA for waveform template matching is characterized by comprising the following steps of: S100, inputting an analog signal, performing ADC (analog-to-digital conversion) processing on the analog signal to obtain an unsigned digital signal, and preprocessing the unsigned digital signal to obtain preprocessed data; S200, carrying out dynamic zero adjustment and whole period extraction on the preprocessed data to obtain the original sampling points of the whole period; s300, carrying out 100-point standardization on the whole period original sampling points to obtain 100-point data, and storing the 100-point data into a dual-port RAM; s400, traversing 100-point data in the dual-port RAM, carrying out normalization processing on the data, and storing the normalization data into the dual-port RAM; S500, loading a COE file, and reading three standard waveforms from the COE file by adopting a pipeline reading architecture; S600, matching the normalized data with the three paths of standard waveforms to obtain three paths of SADs, triggering quick matching and locking corresponding waveform types if one path of SADs is smaller than a threshold value, updating the minimum SADs of all paths and corresponding group numbers if all paths of SADs are smaller than the threshold value, and entering the next group judgment until all groups of normalized data are traversed; And S700, if the normalization data of all groups are judged, the global minimum value and the corresponding waveform of the SAD are screened out from all SADs, and a calibration trigger signal is generated to return to S200.
  2. 2. The method for realizing waveform recognition based on waveform template matching of the FPGA according to claim 1, wherein the COE file is obtained by the following steps: a, setting initial parameters, wherein the initial parameters comprise sampling frequency, frequency range, frequency interval, single-period point number, data bit width, normalized maximum value and waveform core function; b, traversing the frequency sequence according to the initialization parameters so as to generate a waveform sequence of a plurality of frequencies under each type; c, carrying out normalization processing on each frequency waveform sequence by using a normalization maximum value, and splicing all waveform sequences according to a preset sequence to obtain a standard waveform template; And d, generating a COE file meeting the initialization requirement of the FPGA BRAM by using the standard waveform template.
  3. 3. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S100 comprises: s110, inputting an analog signal, and quantizing the analog signal into an 8-bit unsigned digital signal by using an ADC; S120, inputting the unsigned digital signal into an FPGA through an IO interface, and writing the unsigned digital signal into a deep asynchronous FIFO by the FPGA in real time; S130, carrying out synchronous jitter removal processing on the unsigned digital signals in the FIFO through a 3-stage register to obtain preprocessed data.
  4. 4. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S200 comprises: S210, acquiring the preprocessing data output by the FIFO in real time through a parallel comparator array, synchronously extracting extreme values in the preprocessing data, calculating dynamic zero points according to the extreme values, and calibrating the preprocessing data based on the dynamic zero points to obtain calibration data; S220, positioning the cycle starting point of the calibration data by adopting a combination mode of candidate point detection and multi-sampling point verification, outputting cycle starting point pulse to trigger a 32-bit counter to start accumulation, and synchronously starting writing data between effective zero crossing points into the DDR4 to obtain the original sampling point number of the whole cycle.
  5. 5. The method for realizing waveform recognition based on FPGA waveform template matching as set forth in claim 4, wherein, The extremum in S210 includes a sampling maximum value and a sampling minimum value, and the dynamic zero point calculation formula is expressed as: In which, in the process, For a dynamic zero point, For the maximum value of the samples to be sampled, Is the sampling minimum; S220 includes: s221, comparing continuous sampling points in real time through two parallel comparators And And (3) with When meeting the relation of And is also provided with Time stamp Is the candidate point, and then the continuous 3 sampling points after the candidate point Verification, if all of them meet Then confirm the candidate point as effective zero crossing point and output cycle start pulse ; S222, period start pulse Triggering a 32-bit counter to start accumulating, simultaneously starting writing data from the previous effective zero crossing point to the current effective zero crossing point into DDR4, stopping counting until the next effective zero crossing point is detected, stopping writing, and obtaining the original sampling point number of the whole period 。
  6. 6. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S300 includes: S310, when the original sampling point number of the whole period When the step length is calculated by a hardware divider According to the formula Generating 100 intercepting indexes, reading data according to the indexes, and storing the data into an on-chip dual-port RAM; s320, when When it will The point data is written into a 1K depth FIFO and configured into a cyclic output mode, and is formulated by a hardware interpolator And generating 100-point data, and storing the 100-point data into the on-chip dual-port RAM after synchronization.
  7. 7. The method for implementing waveform recognition based on FPGA waveform template matching of claim 6, wherein S400 comprises: S410, traversing 100-point data in the dual-port RAM by adopting a parallel comparator, and extracting a maximum value and a minimum value in 10 clock cycles through two-stage logic of packet comparison and global comparison; and S420, normalizing the 100-point data according to whether the maximum value is equal to the minimum value to obtain normalized data, storing the normalized data into a matched data register set, or outputting an amplitude abnormality mark to trigger returning to S100.
  8. 8. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S500 includes: s510, loading a COE file, wherein the COE file comprises three waveform types, each waveform type corresponds to a plurality of groups of 100-point standard template libraries, each waveform type is independently stored in a BRAM array in a partitioned manner, and each group of 100-point standard template libraries corresponds to 1 frequency point; S520, synchronously reading standard waveforms from the BRAM array by adopting a pipeline reading architecture, and distributing the standard waveforms to three computing units through three independent buses until 100 points in all groups are traversed.
  9. 9. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S600 includes: S610, synchronously calculating the difference value between the normalized data and the corresponding standard waveform by using three calculation units, and converting the difference value into an 8-bit unsigned value absolute difference value by an absolute value circuit; s620, continuously accumulating the absolute differences of the current group by utilizing each calculation unit to obtain three SADs; S630, judging whether three paths of SADs of the current group are smaller than a preset threshold value or not according to the current group, if so, generating a quick matching signal, locking a corresponding waveform type, suspending pipeline reading, and if not, comparing the three paths of SADs of the current group with the minimum SAD value of each path of waveform stored in a history minimum SAD register, and updating the history minimum SAD of each path of waveform and the corresponding group number by utilizing a comparison result.
  10. 10. The method for implementing waveform recognition based on FPGA waveform template matching according to claim 1, wherein S700 includes: s710, if all the groups of normalized data are judged, screening global minimum values and corresponding waveforms of SADs from all the SADs; s720, outputting a corresponding waveform type and a valid mark according to the historical minimum SAD and the corresponding group number, and generating a calibration trigger signal; and S730, based on the calibration trigger signal, driving the FPGA to return to S200 and entering a next pipeline flow.

Description

Waveform recognition implementation method for waveform template matching based on FPGA Technical Field The application belongs to the technical field of signal identification, and particularly relates to a waveform identification implementation method for waveform template matching based on an FPGA. Background Waveform identification is a core technology in the field of electronic information, is widely applied to scenes such as industrial control, communication demodulation, portable detection and the like, and has the core requirements of accurately judging waveform types and extracting parameters, and meanwhile, the requirements of instantaneity, miniaturization and anti-interference performance are met. The development of portable equipment, the high-speed signal scene (such as 20MHz sampling rate) is urgent to microsecond identification response requirements, so that the fusion of platforms such as a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a single chip Microcomputer (MCU) and the like and an identification algorithm is promoted, but the existing scheme still has a significant bottleneck. The current waveform identification technology faces three major core challenges, namely insufficient scene suitability, difficulty in supporting custom waveform identification, limited miniaturized deployment, outstanding contradiction between resource occupation and calculation power requirements, poor real-time performance and incapability of meeting the requirements on processing delay in a high-speed signal scene. The current mainstream waveform recognition scheme is mainly realized based on a singlechip, a digital signal Processor (DIGITAL SIGNAL Processor, DSP), a central processing unit (Central Processing Unit, CPU)/a graphic Processor (Graphics Processing Unit, GPU) and a hardware template matching platform. However, the related technical schemes have significant disadvantages in terms of cost, instantaneity, suitability and resource occupation: 1) The single chip microcomputer/DSP platform has the defects that the performance improvement depends on increasing the clock frequency, increasing the number of boards and expanding the core number, and has obvious limitations. The clock frequency is increased to lead to rapid rise of power consumption and increase of heat dissipation pressure, the complexity of hardware design is increased, meanwhile, the stability of a system is reduced, for example, an STM32H7 frequency is increased to 480MHz, extra heat dissipation fins are needed, the number of boards is increased to increase the cost of equipment, the scheduling coordination and data synchronization technology among multiple boards is high, performance bottlenecks are easy to form, even after optimization, a serial processing architecture still cannot meet microsecond identification requirements of a 20MHz signal, and single-path identification delay is generally more than 1ms. 2) The CPU/GPU platform and the deep learning scheme have the defects that a server based on the CPU/GPU is high in purchasing cost and maintenance cost, high in economic burden in high-performance cluster deployment, most algorithms are written by adopting a traditional serial C/C++, 100-point data are processed in hundreds of microseconds, the efficiency is low in large-scale data processing, the deep learning scheme is supported by a GPU or an AI acceleration card, model parameters such as ResNet and the like are millions, the memory is occupied by over 100MB, small-sized equipment such as a mobile terminal and the like cannot be adapted, and at least 10 tens of thousands of labeling data are required for training. Disclosure of Invention In order to solve the problems in the prior art, the application provides a waveform identification implementation method based on FPGA waveform template matching. The technical problems to be solved by the application are realized by the following technical scheme: the waveform recognition implementation method based on the FPGA for waveform template matching comprises the following steps: S100, inputting an analog signal, performing ADC (analog-to-digital conversion) processing on the analog signal to obtain an unsigned digital signal, and preprocessing the unsigned digital signal to obtain preprocessed data; S200, carrying out dynamic zero adjustment and whole period extraction on the preprocessed data to obtain the original sampling points of the whole period; s300, carrying out 100-point standardization on the whole period original sampling points to obtain 100-point data, and storing the 100-point data into a dual-port RAM; s400, traversing 100-point data in the dual-port RAM, carrying out normalization processing on the data, and storing the normalization data into the dual-port RAM; S500, loading a COE file, and reading three standard waveforms from the COE file by adopting a pipeline reading architecture; S600, matching the normalized data with the three pa