CN-122020642-A - Parallel cut-integrated simplification method based on fault tree logic embedded neural network

CN122020642ACN 122020642 ACN122020642 ACN 122020642ACN-122020642-A

Abstract

A parallel cut-and-integrate simplification method based on a fault tree logic embedded neural network relates to the field of fault tree analysis. In order to solve the problems that in the prior art, the calculation amount of the cut-and-integrate simplification is exponentially increased, the parallelization degree is insufficient, the efficiency is low due to the dependence on explicit comparison, and the cut-and-integrate simplification is difficult to realize on a GPU architecture, the invention provides a high-efficiency cut-and-integrate simplification scheme which utilizes the combination of fault tree logic and a neural network structure. The method comprises the steps of vectorizing an initial cut set, grouping the initial cut set according to orders, generating a corresponding subset base matrix, generating a subset tensor in batches through an index mask, inputting the subset tensor into a fault tree logic equivalent neural network to execute parallel Boolean judgment, outputting a result of whether the subset triggers a top event, slicing and counting according to the judgment result, and rapidly removing a non-minimum cut set to obtain a minimum cut set. The method is suitable for reliability analysis and safety evaluation of large-scale complex systems such as aerospace, nuclear power, rail transit and petrochemical devices.

Inventors

DING MING
WANG YANKAI
YANG YONGYONG
CAO XIAXIN
MENG ZHAOMING
GUO ZEHUA
HAO XIAOTIAN

Assignees

哈尔滨工程大学

Dates

Publication Date: 20260512
Application Date: 20251223

Claims (9)

1. A parallel cut-and-integrate simplification method based on a fault tree logic embedded neural network is characterized by comprising the following steps: Preprocessing an input initial cut set, converting each cut set into a corresponding 0-1 vector under a fixed basic event sequence, calculating the order of each cut set, sequencing according to the ascending order of the orders, continuously arranging the cut sets with the same order to form same-order groups, and outputting a structured cut set matrix and the number of the cut sets under each order; According to the structured cut set matrix and the number of cut sets under each order, for each candidate cut set, respectively removing any one basic event from the candidate cut set in parallel, and generating all the subsets of the cut set, namely generating all the subset vectors of which the number of the "orders" of all the candidate cut sets is reduced by one after the "1" of a certain position of each candidate cut set vector is changed into the "0" in batch, and generating a matrix composed of the subset vectors of the "orders" of all the candidate cut sets; Inputting the subset matrix into a neural network structure logically equivalent to a fault tree, executing parallel Boolean judgment, outputting a result vector of which each element corresponds to a subset in the input matrix one by one in sequence and the value represents whether the subset triggers a top event or not; Dividing the result vector into continuous slices with the same number as the number of the cut sets according to the result vector and the number of the prerecorded cut sets of each step, judging that the corresponding cut set is a non-minimum cut set to be removed if a result with the value of 1 exists in the slices, otherwise, reserving and identifying the cut set as the minimum cut set, and outputting a final minimum cut set.
2. The parallel cut-collection simplification method based on the fault tree logic embedded neural network according to claim 1, wherein the cut-collection row vectors are subjected to batch replication for the number of orders according to the number of orders of each candidate cut-collection, and the replicated vectors are subjected to stacking operation in a GPU parallel computing architecture, so that each row block of the generated basic matrix is continuously arranged in a storage space.
3. The parallel cut-and-gather simplification method based on the fault tree logic embedded neural network according to claim 1, wherein the element positions to be modified in the matrix are positioned by utilizing the coordination of row coordinates increasing by rows and index vectors, and the values of all marking positions are changed from '1' to '0' through single tensor assignment operation on the GPU.
4. The parallel cut-and-gather simplification method based on the fault tree logic embedded neural network according to claim 1, wherein the fault tree boolean function module equivalent to the neural network is a feed-forward neural network without training, and the logic gate operation of the fault tree is mapped by adopting fixed weight and activation function, so that the input tensor can be forward propagated once on a graphic processor or other parallel acceleration hardware, thereby outputting the judging results of all subsets in parallel.
5. The parallel cut-and-gather simplification method based on the fault tree logic embedded neural network according to claim 1, wherein the output of the neural network equivalent module is a one-dimensional result vector, and the result vector maintains the corresponding relation of the input sequence, so that the index mapping consistency between the subsequent slice and the candidate cut-set group is ensured.
6. The utility model provides a parallel cut collection simplification device based on embedded neural network of fault tree logic which characterized in that includes: The method comprises the steps of preprocessing an input initial cut set, converting each cut set into a corresponding 0-1 vector under a fixed basic event sequence, calculating the order of each cut set, sequencing according to an ascending order of the order, continuously arranging the cut sets with the same order to form same-order groups, and outputting a structured cut set matrix and order information; According to the structured cut set matrix and the order information, for each candidate cut set, respectively removing any basic event from the candidate cut set in parallel, generating all the subsets of the cut set, namely generating all the subset vectors of which the '1' of a certain position of all the candidate cut set vectors is changed into '0', in batches, and generating a module of the matrix formed by the subset vectors of the 'order minus one' of all the candidate cut sets; The module is used for inputting the subset matrix into a neural network structure with the logical equivalent of the fault tree, executing parallel Boolean judgment according to the connection relation of the logic gate of the fault tree and a preset activation function, outputting a result vector of which each element corresponds to a subset in the input matrix one by one and the value represents whether the subset triggers a top event or not; And a module for dividing the result vector into a plurality of continuous slices and executing logic OR operation according to the result vector and the pre-recorded order grouping information, judging that the corresponding cut set is a non-minimum cut set to be removed if a result with the value of 1 exists in any slice, otherwise, reserving and identifying the cut set as the minimum cut set, and outputting a final minimum cut set.
7. Computer storage medium for storing a computer program, characterized in that the computer performs the method of claim 1 when the computer program is read by the computer.
8. A computer comprising a processor and a storage medium, characterized in that the computer performs the method of claim 1 when the processor reads a computer program stored in the storage medium.
9. Computer program product, as a computer program, characterized in that the method of claim 1 is implemented when the computer program is executed.

Description

Parallel cut-integrated simplification method based on fault tree logic embedded neural network Technical Field Relates to the field of fault tree analysis, in particular to a high-efficiency parallelization fault tree cut set solving method. Background Fault tree analysis (FTA for short) is one of the most classical and widely used logic analysis methods in complex system reliability and security assessment. By decomposing the top-level failure event of the system into the bottom-level basic event step by step, a fault tree structure with a hierarchical logic relationship is formed, and potential risk sources and interrelationships of the system can be systematically identified. Particularly in the high-reliability industries of nuclear power, aerospace, rail transit, petrochemical industry, military equipment and the like, fault tree analysis has become an important foundation for quantitative risk assessment and safety decision. In the qualitative analysis process of the fault tree, the solution of a Minimum Cut Set (MCS) is a key link. The minimal cut set is the minimal basic event combination that results in the occurrence of a top event, revealing the most vulnerable failure mode of the system. All the minimum cut sets are rapidly and accurately obtained, and the method has important significance for developing weak link identification, importance analysis, risk control and design optimization of the system. Therefore, efficient solution algorithms around the minimal cut set have been the focus of research in the field of fault tree analysis. The traditional minimum cut set solving method is generally divided into two steps, namely, firstly, an initial cut set containing redundant items is generated through MOCUS algorithm and other methods, and then, simplification is carried out on the set, and non-minimum cut sets are removed. The core basis for simplification is "absorption law", in which if cut set A is a proper subset of cut set B (i.e., all basic events in A are in B and B contains events other than A), then B is the non-minimum cut set and should be "absorbed" by A for elimination. In actual engineering, conventional minimal cut set reduction typically relies on an "absorption law" judgment, i.e., if cut set A is a proper subset of cut set B, then B is absorbed by A and no longer the minimal cut set. The method is strict in logic, but the implementation mode is mainly pair-by-pair comparison, namely, subset relation judgment is carried out on each candidate cut set and all lower-order cut sets, and the calculation complexity is approximately O (N2). When the system scale is increased and the number of cutsets reaches tens of thousands or even hundreds of thousands, the comparison times are increased in square, and the calculation bottleneck is extremely easy to cause. Taking a nuclear power system or an aviation flight control system as an example, a fault tree of the system often comprises tens of thousands of basic events and millions of cutset records, and the traditional algorithm can complete cutset simplification only by taking hours or even days, so that the instantaneity and the engineering application value are seriously influenced. In recent years, some studies have attempted to speed up fault tree analysis using GPU parallel computing. However, the methods are only partially parallel in the Boolean calculation layer, and still need to perform explicit comparison among cutsets, and lack systematic design oriented to the cutset reduction link. Meanwhile, artificial intelligence methods are also tried to be introduced, such as reliability prediction models based on neural networks, but the methods generally rely on data training, cannot ensure the logic certainty and reproducibility of results, and cannot meet the verification and traceability requirements of safety key fields. In summary, in the prior art, the problems of exponential increase of the calculation amount in the cut-set simplification stage, insufficient parallelization degree, low efficiency caused by explicit comparison, and difficulty in efficient implementation on parallel architectures such as a GPU and the like exist, and the efficient minimum cut-set solving requirement of a large-scale complex system is difficult to support. Disclosure of Invention In order to solve the problems of exponential increase of calculation amount, insufficient parallelization degree, low efficiency caused by dependence on explicit comparison and difficulty in efficient realization on parallel architectures such as GPU and the like in the cutting and integrating stage and the technical defect of difficulty in supporting the efficient minimum cutting and integrating solving requirement of a large-scale complex system in the prior art, the invention provides the technical scheme as follows: a parallel cut-and-integrate simplification method based on a fault tree logic embedded neural network comprises the following steps: Preprocessing an