CN-122020737-A - Hybrid reconfigurable PUF circuit, electronic device and method

CN122020737ACN 122020737 ACN122020737 ACN 122020737ACN-122020737-A

Abstract

The application relates to the technical field of integrated circuits, in particular to a hybrid reconfigurable PUF circuit, electronic equipment and a method, wherein the hybrid reconfigurable PUF circuit comprises an SRAM storage unit, the SRAM storage unit comprises a first inverter and a second inverter, the first inverter and the second inverter are in cross coupling, one end of the first RRAM unit is electrically connected with a first power supply access node, the other end of the first RRAM unit is electrically connected with the first inverter, one end of the second RRAM unit is electrically connected with a second power supply access node, and the other end of the second RRAM unit is electrically connected with the second inverter. Therefore, the RRAM is connected in series to the SRAM critical path and a feedback structure is introduced, so that the problems that the stability and the speed of the traditional PUF are difficult to be compatible are solved, and the physical unclonable function circuit which is high in stability, nonvolatile, reconfigurable and has high-speed response and high area efficiency is realized.

Inventors

YAO PENG
LIU KEER
LI XUEQI
PAN SINING
WU DONG
TANG JIANSHI
GAO BIN
QIAN HE
WU HUAQIANG

Assignees

清华大学

Dates

Publication Date: 20260512
Application Date: 20251229

Claims (10)

1. A hybrid reconfigurable PUF circuit, comprising: an SRAM memory cell comprising a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled; one end of the first RRAM unit is electrically connected with the first power supply access node, and the other end of the first RRAM unit is electrically connected with the first inverter; and one end of the second RRAM unit is electrically connected with the first power supply access node, and the other end of the second RRAM unit is electrically connected with the second inverter.
2. The hybrid reconfigurable PUF circuit of claim 1, further comprising: A feedback resistor, one end of which is electrically connected with the first bit line, and the other end of which is electrically connected with the second bit line, The feedback resistor is configured to adjust a voltage across the first RRAM cell if the first RRAM cell is configured, or adjust a voltage across the second RRAM cell if the second RRAM cell is configured.
3. The hybrid reconfigurable PUF circuit of claim 1, wherein the first and second RRAM cells are integrated in a later metal layer of the SRAM memory cell.
4. The hybrid reconfigurable PUF circuit of claim 1, wherein the first inverter includes a first MOS transistor, a second MOS transistor, and a first not gate, wherein, The grid electrode of the first MOS tube is electrically connected with one end of the first NOT gate, the source electrode of the first MOS tube is electrically connected with the first RRAM unit, and the drain electrode of the first MOS tube is electrically connected with the source electrode of the second MOS tube; The other end of the first NOT gate is electrically connected with the grid electrode of the second MOS tube and the second inverter respectively; And the drain electrode of the second MOS tube is electrically connected with a second power supply access node.
5. The hybrid reconfigurable PUF circuit of claim 4, wherein the second inverter includes a third MOS transistor, a fourth MOS transistor, and a second not gate, wherein, The grid electrode of the third MOS tube is electrically connected with one end of the second NOT gate, the source electrode of the third MOS tube is electrically connected with the second RRAM unit, and the drain electrode of the third MOS tube is electrically connected with the source electrode of the fourth MOS tube; the other end of the second NOT gate is electrically connected with the grid electrode of the fourth MOS tube, the drain electrode of the first MOS tube and the source electrode of the second MOS tube respectively; And the drain electrode of the fourth MOS tube is electrically connected with the second power supply access node.
6. The hybrid reconfigurable PUF circuit of claim 5, wherein the first and third MOS transistors are PMOS transistors and the second and fourth MOS transistors are NMOS transistors.
7. The hybrid reconfigurable PUF circuit of claim 6, further comprising: The first end of the fifth MOS tube is electrically connected with the connecting node between the first MOS tube and the second MOS tube, the second end of the fifth MOS tube is electrically connected with the first bit line, and the control end of the fifth MOS tube is electrically connected with the first word line; and the first end of the sixth MOS tube is electrically connected with the connecting node between the third MOS tube and the fourth MOS tube, the second end of the sixth MOS tube is electrically connected with the second bit line, and the control end of the sixth MOS tube is electrically connected with the first word line.
8. An electronic device comprising a hybrid reconfigurable PUF circuit as in any one of claims 1-7.
9. A hybrid reconfigurable PUF method, applied to a hybrid reconfigurable PUF circuit according to any one of claims 1-7, wherein the method comprises the steps of: Setting a first bit line and a second bit line of the hybrid reconfigurable PUF circuit as a first reference potential, applying a first pulse signal to a first power supply access node, and executing FORMING operations on a first RRAM unit and a second RRAM unit in parallel based on the first pulse signal to convert the first RRAM unit and the second RRAM unit into a resistance variable state; Electrically connecting the first bit line and the second bit line, and applying a second reference potential to the first bit line and the second bit line to apply a second pulse signal to the first power access node and perform a SET operation on the first RRAM cell and the second RRAM cell based on the second pulse signal and on the second pulse signal, thereby transitioning the first RRAM cell and the second RRAM cell to complementary resistive states in the presence of a positive feedback effect between the first bit line and the second bit line; And setting the first power access node and the second bit line as a third reference potential, applying a third pulse signal to a target bit line, generating a unidirectional conductive path passing through the RRAM cell corresponding to the target bit line, executing a RESET operation on the RRAM cell corresponding to the target bit line, and recovering the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state.
10. The method of claim 9, wherein applying a third pulse signal to a target bit line to generate a unidirectional conductive path through the RRAM cell corresponding to the target bit line, performing a RESET operation on the RRAM cell corresponding to the target bit line, and restoring the resistance state of the RRAM cell corresponding to the target bit line to a preset resistance state, comprises: When the target bit line is a first bit line, applying the third pulse signal to the first bit line, generating a unidirectional conductive path passing through the first RRAM cell, executing a RESET operation on the first RRAM cell, and recovering the resistance state of the first RRAM cell to a preset resistance state; And/or when the target bit line is a second bit line, applying the third pulse signal to the second bit line, generating a unidirectional conductive path passing through the second RRAM cell, executing a RESET operation on the second RRAM cell, and recovering the resistance state of the second RRAM cell to a preset resistance state.

Description

Hybrid reconfigurable PUF circuit, electronic device and method Technical Field The present application relates to the field of integrated circuits, and in particular, to a hybrid reconfigurable PUF circuit, an electronic device, and a method. Background The physical unclonable function (Physical Unclonable Function, PUF) is a hardware security technique that exploits microscopic random deviations inherent in semiconductor manufacturing processes to generate a chip unique identity. The method is widely applied to security scenes such as key generation, equipment authentication, copyright protection and the like due to the characteristics of true randomness, unclonability, low cost and the like. The traditional PUF structure is mostly realized based on a single unit such as SRAM, RRAM, ring oscillator or arbiter, and has the limitations of insufficient response stability, high hardware cost, non-reconfigurability and the like. In the related art, as shown in fig. 1, fig. 1 is a schematic diagram of a PUF basic structure based on SRAM in the related art, and a conventional PUF basic structure based on SRAM uses a random initial state caused by process deviation in a power-on process of an SRAM cell as a response signal, so that the PUF basic structure based on SRAM has the advantages of high response speed and high integration level. However, the volatility of SRAM itself makes it impossible to maintain state after power-down, and the response needs to be randomly generated again each time power is applied, so that PUF output stability is limited and sensitivity to environmental fluctuations and aging effects is high. On the other hand, RRAM is also used as an emerging nonvolatile memory for realizing a PUF circuit, and the typical structure is shown in FIG. 2, and FIG. 2 is a schematic diagram of a typical structure for realizing the PUF circuit in RRAM in the related art, and the stability of the PUF is obviously improved by virtue of the nonvolatile characteristic of RRAM. However, the read-write speed of RRAM is generally lower than that of SRAM, and the cell area and the manufacturing cost are relatively high, which limits the popularization potential in high-performance and low-cost applications to a certain extent, and needs to be solved. Disclosure of Invention The application provides a hybrid reconfigurable PUF circuit, electronic equipment and a method, which are used for solving the problems that the stability and the speed of the traditional PUF are difficult to be compatible. An embodiment of a first aspect of the present application provides a hybrid reconfigurable PUF circuit, comprising: an SRAM memory cell comprising a first inverter and a second inverter, the first inverter and the second inverter being cross-coupled; one end of the first RRAM unit is electrically connected with the first power supply access node, and the other end of the first RRAM unit is electrically connected with the first inverter; and one end of the second RRAM unit is electrically connected with the first power supply access node, and the other end of the second RRAM unit is electrically connected with the second inverter. Optionally, the method further comprises: A feedback resistor, one end of which is electrically connected with the first bit line, and the other end of which is electrically connected with the second bit line, The feedback resistor is configured to adjust a voltage across the first RRAM cell if the first RRAM cell is configured, or adjust a voltage across the second RRAM cell if the second RRAM cell is configured. Optionally, the first and second RRAM cells are integrated in a later metal layer of the SRAM memory cell. Optionally, the first inverter comprises a first MOS tube, a second MOS tube and a first NOT gate, wherein, The grid electrode of the first MOS tube is electrically connected with one end of the first NOT gate, the source electrode of the first MOS tube is electrically connected with the first RRAM unit, and the drain electrode of the first MOS tube is electrically connected with the source electrode of the second MOS tube; The other end of the first NOT gate is electrically connected with the grid electrode of the second MOS tube and the second inverter respectively; And the drain electrode of the second MOS tube is electrically connected with a second power supply access node. Optionally, the second inverter comprises a third MOS tube, a fourth MOS tube and a second NOT gate, wherein, The grid electrode of the third MOS tube is electrically connected with one end of the second NOT gate, the source electrode of the third MOS tube is electrically connected with the second RRAM unit, and the drain electrode of the third MOS tube is electrically connected with the source electrode of the fourth MOS tube; the other end of the second NOT gate is electrically connected with the grid electrode of the fourth MOS tube, the drain electrode of the first MOS tube and the source electrode of th