CN-122020738-A - Configurable time delay transient effect ring oscillator PUF

CN122020738ACN 122020738 ACN122020738 ACN 122020738ACN-122020738-A

Abstract

The invention discloses a configurable delay transient effect ring oscillator (PUF), which comprises two NAND gates, two groups of configurable delay units, wherein one input end of each of the first NAND gate and the second NAND gate is used for inputting an enabling signal, each group of configurable delay units consists of n configurable delay units which are connected in series, the output end of each of the first NAND gates is connected with the first group of the configurable delay units, the output end of each of the first group of the configurable delay units is connected with the other input end of the second AND gate, the output end of each of the second AND gates is connected with the second group of the configurable delay units, and the output end of each of the second group of the configurable delay units is connected with the other input end of the first NAND gate, wherein the configurable delay units are configured to have different delays based on an excitation signal. By utilizing nonlinear dynamic behavior reflected by cycle collapse count CTC in TERO oscillation process, an oscillation path configuration and an adjustable delay mechanism related to excitation are introduced, and a modeling attack resistant PUF architecture with low resource overhead and high nonlinearity is constructed.

Inventors

NI TIANMING
LIU HUAN
BIAN JINGCHANG
Nie Mu
WU HAO
HU ANG
LIU YUN
LIU JINGJING
LIU DONGSHENG

Assignees

安徽工程大学

Dates

Publication Date: 20260512
Application Date: 20260116

Claims (9)

1. A configurable time delay transient effect ring oscillator PUF, the PUF comprising: the two NAND gates comprise a first NAND gate and a second NAND gate, and one input end of the first NAND gate and one input end of the second NAND gate are used for inputting an enabling signal; The output end of the first NAND gate is connected with the other input end of the second NAND gate, the output end of the second NAND gate is connected with the second configurable delay unit, and the output end of the second configurable delay unit is connected with the other input end of the first NAND gate; wherein the configurable delay unit is configured to have different time delays based on the excitation signal configuration.
2. The configurable delay transient ring oscillator PUF of claim 1, wherein the configurable delay unit comprises a configurable delay unit I and/or a configurable delay unit II; the delay time of the configurable delay unit I and the configurable delay unit II under different excitation bits is different.
3. The configurable time delay transient effect ring oscillator PUF of claim 1, wherein the configurable delay unit I comprises: The output end of the OR gate and the output end of the first exclusive OR gate are connected with the AND gate, and the output end of the AND gate and the output end of the excitation signal are connected with the second exclusive OR gate.
4. A configurable delay transient ring oscillator PUF according to claim 3, characterized in that the input stimulus bit C i = 1, the configurable delay unit I has an inverter function, the input stimulus bit C i = 0, the configurable delay unit I has a buffer function, wherein the delay of the configurable delay unit I at the stimulus bit C i = 1 is smaller than the stimulus bit C i = 0.
5. The configurable time delay transient effect ring oscillator PUF of claim 1, wherein the configurable delay unit II comprises: The output end of the AND gate, the output end of the first exclusive OR gate are connected with the OR gate, and the output end of the OR gate and the output end of the excitation signal are connected with the second exclusive OR gate.
6. The configurable delay transient ring oscillator PUF of claim 5, wherein the input stimulus bit C i = 0, the configurable delay unit II has an inverter function, the input stimulus bit C i = 1, and the configurable delay unit II has a buffer function, wherein the configurable delay unit II has a delay less than the stimulus bit C i = 1 at the stimulus bit C i = 0.
7. The configurable delay transient ring oscillator PUF of claim 1, wherein when the configurable delay unit comprises a configurable delay unit I and a configurable delay unit II, the delay unit I is connected end-to-end with the configurable delay unit II.
8. A method for excitation signal selection of a configurable time delay transient effect ring oscillator PUF according to any one of claims 1 to 7, characterized in that the method is in particular as follows: (1) Deleting from the original excitation set excitations sensitive to environmental fluctuations; (2) Extracting the current neighboring excitation sequentially from the original excitation set Calculating the current adjacent excitation Counting the absolute value of the difference value of the CTC in the breakdown period under the basic environment; (3) If the absolute value of the difference is smaller than the set difference threshold, deleting the excitation from the original excitation set Excitation Order-making Step (2) is performed until the traversal of the original stimulus set is completed.
9. The excitation signal selection method according to claim 8, wherein the method of determining the excitation sensitive to environmental fluctuations is specifically as follows: Computing the ith stimulus in the stimulus set Environmental fluctuations of (a) In the environment wave Greater than the environmental tolerance threshold Then the excitation is identified Sensitivity to environmental fluctuations, wherein the environmental fluctuations The calculation formula is as follows: ; Wherein, the Representing that the ith stimulus in the stimulus set is in the basic environment The next collapse period count is taken, Representing that the ith stimulus in the stimulus set is in an extreme environment The next collapse period counts.

Description

Configurable time delay transient effect ring oscillator PUF Technical Field The invention belongs to the technical field of PUF circuits, and particularly relates to a configurable time delay transient effect ring oscillator PUF. Background The physical unclonable function (Physical Unclonable Functions, PUF) is a type of hardware-based security primitive that relies on random manufacturing variations that naturally occur in CMOS processes to generate unique and unpredictable physical characteristics for each chip. When the PUF circuit is externally excited, a corresponding stimulus-Response pair (Challeng-Response Paris, CRP) is output. The response is derived from small and uncontrollable process differences of transistor threshold values, circuit linewidths, interconnection parasitic parameters and the like, so that different chips can generate different outputs under the same excitation to form unique hardware 'fingerprints'. These random fluctuations, which are generated during the manufacturing process, are inherently unpredictable and unclonable and become the core support for the natural properties of the PUF. Even if an attacker utilizes advanced physical attack or reverse engineering and other means, the complex internal mechanism cannot be accurately reconstructed at the physical layer, and the irreversible physical layer safety characteristic enables the PUF to evolve into a high-performance and high-reliability hardware safety primitive in the ecology of the Internet of things, thereby becoming a key root of trust for maintaining the identity authenticity of mass terminal equipment. According to the space size of CRPs, the Physical Unclonable Functions (PUFs) are generally classified into a Weak PUF (Weak PUF) and a strong PUF (Strong PUF), and the number of CRPs of the strong PUFs grows exponentially with the circuit scale and is widely applied to identity authentication of internet of things equipment. Arbiter PUF (APUF) is the earliest and most popular strong PUF circuit that produces a large number CRPs by selecting a symmetric delay path at each stage. So far, researchers have conducted a great deal of research on strong PUFs, the strong PUF structure typified by APUF being the first and most widely used structure at present, APUF generating a massive excitation response by selecting a symmetric delay path at each Stage (CRPs). While its elaborate symmetrical architecture contributes to the exponential expansion of CRPs, it is contradictory that since its underlying physical properties depend on a linear additive delay model, there is a significant linear correlation between the large number of CRPs of APUF, and an attacker can model the internal circuitry of the PUF after CRPs is acquired, through its internal correlation, to predict the others CRPs. Disclosure of Invention The present invention provides a configurable time delay transient effect ring oscillator PUF, which aims to solve at least one of the above problems. The invention is realized in that a configurable time delay transient effect ring oscillator PUF, the PUF comprising: the two NAND gates comprise a first NAND gate and a second NAND gate, and one input end of the first NAND gate and one input end of the second NAND gate are used for inputting an enabling signal; The output end of the first NAND gate is connected with the other input end of the second NAND gate, the output end of the second NAND gate is connected with the second configurable delay unit, and the output end of the second configurable delay unit is connected with the other input end of the first NAND gate; wherein the configurable delay unit is configured to have different time delays based on the excitation signal configuration. Further, the configurable delay unit comprises a configurable delay unit I and/or a configurable delay unit II; the delay time of the configurable delay unit I and the configurable delay unit II under different excitation bits is different. Further, the configurable delay unit I includes: The output end of the OR gate and the output end of the first exclusive OR gate are connected with the AND gate, and the output end of the AND gate and the output end of the excitation signal are connected with the second exclusive OR gate. Further, the input driving bit C i =1, the configurable delay unit I has an inverter function, the input driving bit C i =0, and the configurable delay unit I has a buffer function, wherein the delay of the configurable delay unit I when driving bit C i =1 is smaller than the delay of driving bit C i =0. Further, the configurable delay unit II includes: The output end of the AND gate, the output end of the first exclusive OR gate are connected with the OR gate, and the output end of the OR gate and the output end of the excitation signal are connected with the second exclusive OR gate. Further, the input driving bit C i =0, the configurable delay unit II has an inverter function, the input driving bit C i =1, a