CN-122021172-A - Packaging scheme screening method based on chip warpage simulation prediction

CN122021172ACN 122021172 ACN122021172 ACN 122021172ACN-122021172-A

Abstract

The invention provides a packaging scheme screening method based on chip warpage simulation prediction, which comprises the steps of establishing a chip simulation model based on a conventional packaging structure by adopting a finite element analysis technology, respectively carrying out dynamic thermomechanical analysis test and thermomechanical analysis test on entity samples corresponding to each structure of the model so as to determine core parameters such as viscoelastic parameters, thermal expansion coefficients and the like of the entity samples, inputting parameters required by each structure of the model, setting model constraint and load, carrying out finite element analysis solution, carrying out warpage test on prototype samples corresponding to the simulation model, comparing simulation results, judging whether calculation errors exceed an allowable threshold value, establishing an accurate simulation model and running simulation according to an ultrathin packaging structure scheme, and comparing the warpage results of the accurate simulation model under different structure-material combinations so as to screen out an optimal inhibition scheme for the warpage of the ultrathin packaging chip. The method provided by the invention is more efficient, improves the screening efficiency, and meets the research and development and production requirements of ultrathin packaged chips.

Inventors

CHEN HONGTAO
WANG PEIZHONG
ZHANG YIHAO
WANG BIN
BAI JIARUI
LI JUANJUAN

Assignees

哈尔滨工业大学(深圳)(哈尔滨工业大学深圳科技创新研究院)
深圳市晶存科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260206

Claims (8)

1. A packaging scheme screening method based on chip warpage simulation prediction is characterized by comprising the following steps: step S1, a chip simulation model based on a conventional packaging structure is established by adopting a finite element analysis technology; S2, respectively carrying out dynamic thermomechanical analysis test and thermomechanical analysis test on the entity samples corresponding to each structural layer of the chip simulation model, and measuring the viscoelasticity modulus and the thermal expansion coefficient of the entity samples; S3, inputting the measured material parameters of each structural layer into the chip simulation model, setting model constraint and load conditions, and carrying out finite element analysis and solving to obtain simulation warp data of a conventional packaging structure; S4, performing warping test on the prototype sample corresponding to the conventional packaging structure to obtain actual measurement warping data, comparing the simulation warping data with the actual measurement warping data, calculating an error, and judging that the model parameters are accurate if the error does not exceed a preset threshold; Step S5, establishing a corresponding accurate simulation model according to at least one ultra-thin packaging structure scheme, and inputting the material parameters of each structural layer verified in the step S4 for finite element analysis to obtain a simulation warping result of the ultra-thin packaging scheme; And S6, comparing the warping results of the accurate simulation models under different structure-material combination schemes, and screening out an optimized ultrathin packaging scheme for realizing optimal warping inhibition.
2. The method for packaging scheme screening based on chip warpage simulation prediction as claimed in claim 1, wherein the step S1 comprises the step of constructing an equivalent three-dimensional simulation model by referring to the actual size of a chip with a conventional packaging structure in a ratio of 1:1.
3. The method for screening packaging schemes based on chip warpage simulation prediction as set forth in claim 1, wherein the step S2 includes: Applying periodic deformation to the material at a controlled temperature and frequency through dynamic thermo-mechanical analysis test, measuring stress response of the material, and calculating to obtain storage modulus, loss modulus and loss factor of the material; And applying constant micro load to the sample at a controlled temperature through a thermal mechanical analysis test, recording the variation of the length of the sample along with the temperature, and calculating to obtain the linear thermal expansion coefficients of the material in different temperature ranges.
4. The method for screening packaging schemes based on chip warpage simulation prediction as set forth in claim 1, wherein the step S3 includes: Step S31, inputting material parameters of each structural layer, including viscoelastic modulus, thermal expansion coefficient and Poisson ratio; in the method, a three-dimensional simulation model is subjected to a sub-step S32, wherein boundary conditions of the model are set, including contact conditions, ambient temperature, thermal conditions and fixed constraints, a sub-step S33, wherein the three-dimensional simulation model is subjected to grid division to generate a finite element grid, and a sub-step S34, wherein finite element calculation is performed and a numerical result is derived.
5. The method for packaging scheme screening based on chip warpage simulation prediction as set forth in claim 1, wherein the step S4 includes: Step S41, performing a warp test on the prototype sample to obtain warp actual measurement data of the prototype sample under a specified environmental condition, step S42, calculating deviation between the simulated warp data and the warp actual measurement data, judging whether the deviation exceeds a preset allowable threshold, step S5, if the deviation does not exceed the allowable threshold, checking links of dynamic thermal mechanical analysis test, model construction and boundary condition setting, and re-executing step S3 after correction.
6. The method for screening a packaging scheme based on simulation prediction of chip warpage according to claim 1, further comprising determining a plurality of alternative structure-material combination schemes of an ultra-thin packaging structure before performing the step S5, wherein material parameters required for constructing the accurate simulation model are obtained from conventional simulation model parameters, dynamic thermo-mechanical analysis tests or thermo-mechanical analysis test results verified by the step S4.
7. The method for packaging scheme screening based on chip warpage simulation prediction as claimed in claim 1, wherein the step S5 comprises the following sub-steps: S51, constructing an accurate simulation model according to the selected ultrathin packaging structure scheme in a ratio of 1:1; Step S52, inputting material parameters required by each structural layer; step S53, carrying out grid division on the accurate simulation model to generate a finite element grid; In a substep S54, finite element calculations are performed and simulated warp results are derived.
8. The method for screening packaging schemes based on chip warpage simulation prediction as claimed in claim 1, wherein the step S6 comprises comparing and analyzing the warpage results of the accurate simulation model under different structure-material combinations, and screening out an optimal ultrathin packaging scheme with the goal of minimizing warpage, so as to realize active prediction and control of chip warpage from a design end.

Description

Packaging scheme screening method based on chip warpage simulation prediction Technical Field The invention relates to the technical field of advanced electronic packaging, in particular to a packaging scheme screening method based on chip warpage simulation prediction. Background Along with the accelerated development of the semiconductor technology towards high density, miniaturization and frivolity, the ultrathin packaging chip has the outstanding advantages of small volume, light weight, excellent electrical performance and the like, and is widely applied to miniature electronic products such as smart phones, wearable equipment, terminals of the Internet of things and the like. In order to achieve the ultrathin packaging structure, engineering practice is generally started from the thickness of materials, and three technical paths are mainly adopted, namely the thickness of a substrate is reduced, the thickness of a plastic sealing layer is compressed, and the height of a solder ball bump is reduced. However, in the process of manufacturing, packaging and service of an ultrathin packaged chip, warpage deformation is extremely easy to be caused due to the coupling effect of multiple factors such as mismatching of thermal expansion coefficients of materials of all structural layers, process temperature fluctuation, packaging residual stress accumulation and the like. In addition, the warpage risk is further exacerbated by the size effect of the ultra-thin structure, which places higher demands on the accuracy of the package design. The warp deformation of the chip can cause poor lamination of the chip and the substrate and bonding failure, thereby affecting packaging reliability, even causing the problems of chip circuit damage, package cracking and the like, directly reducing the product yield and the service life, and finally causing the failure of terminal equipment. Therefore, the warping behavior of the ultrathin packaged chip can be accurately predicted in the design stage, and the structure-material combination scheme capable of improving the warping is screened according to the warping behavior, so that the warping behavior is very important for optimizing the package design and improving the reliability of products. At present, the research on the warpage behavior of a chip mainly depends on two means of experimental test and simulation prediction. Although the experimental test method (such as Shadow Moire) can acquire real data, the experimental test method has the limitations of long period, high cost, certain destructiveness and the like, and is difficult to compare the inhibition effect of different structure-material combinations on warpage in the design stage, so that the requirements of efficient research and development cannot be met. In contrast, the simulation prediction method has the advantages of low cost, high efficiency, strong repeatability and support of batch comparison analysis, and has become the main stream direction for chip warpage research and package scheme optimization. However, the acquisition and matching of input parameters (e.g., material thermal expansion coefficient, elastic modulus, etc.) in the simulation are often not accurate enough, resulting in difficulty in achieving high-precision prediction of warp behavior. Therefore, aiming at the characteristics of the ultrathin packaging chip, an accurate and efficient ultrathin packaging scheme screening method based on chip warpage simulation prediction is developed to solve the problems of insufficient simulation precision, limited applicability and the like in the prior art, and meets the research and development and production requirements of the ultrathin packaging chip, so that the method has become a key technical problem to be overcome in the field. Disclosure of Invention Aiming at the technical problems, the invention discloses a packaging scheme screening method based on chip warpage simulation prediction, which utilizes finite element analysis and is verified through fusion entity sample parameter test to realize accurate prediction of chip warpage behavior, thereby efficiently screening out a structure-material combination scheme with improved warpage and meeting the research and development and production requirements of ultrathin packaging chips. In this regard, the invention adopts the following technical scheme: A packaging scheme screening method based on chip warpage simulation prediction comprises the following steps: step S1, a chip simulation model based on a conventional packaging structure is established by adopting a finite element analysis technology; S2, respectively carrying out dynamic thermomechanical analysis test and thermomechanical analysis test on the entity samples corresponding to each structural layer of the chip simulation model, and measuring the viscoelasticity modulus and the thermal expansion coefficient of the entity samples; S3, inputting the measured material parameters o