Search

CN-122021492-A - Instruction generation method, device, equipment and storage medium

CN122021492ACN 122021492 ACN122021492 ACN 122021492ACN-122021492-A

Abstract

The application discloses a method, a device, equipment and a storage medium for generating instructions, and belongs to the technical field of artificial intelligent chips. The method comprises the steps of obtaining task verification information of a target object, wherein the task verification information comprises task information of a plurality of subtasks of the target object, analyzing association relations among the subtasks according to the task information of the subtasks to obtain association relation analysis results, selecting a target operator capable of executing the subtasks from a plurality of preset operators based on the task information corresponding to each subtask, generating an instruction set corresponding to the subtask according to resources required by an execution process of the target operator, simulating the process of executing the subtask by the target operator through instructions in the instruction set, generating a target instruction set based on the instruction set corresponding to the subtasks and the association relation analysis results, and verifying the target object to the target task through instructions in the target instruction set, so that verification efficiency is improved.

Inventors

  • Request for anonymity
  • Request for anonymity

Assignees

  • 上海壁仞科技股份有限公司

Dates

Publication Date
20260512
Application Date
20260122

Claims (10)

  1. 1. A method of generating instructions, the method comprising: Task verification information of a target object is obtained, wherein the task verification information comprises task information of a plurality of subtasks of the target task, and the task information of each subtask comprises task input information and task output information; According to the task information of the plurality of subtasks, the association relation among the plurality of subtasks is analyzed, and an association relation analysis result is obtained; Selecting a target operator capable of executing the subtask from a plurality of preset operators based on task information corresponding to each subtask, and generating an instruction set corresponding to the subtask according to resources required by an execution process of the target operator, wherein an instruction in the instruction set is used for simulating the execution process of the subtask by the target operator; And generating a target instruction set based on the instruction sets corresponding to the plurality of subtasks and the association relation analysis result, wherein the instructions in the target instruction set are used for verifying the verification result of the target object on the target task.
  2. 2. The method of claim 1, wherein selecting a target operator capable of executing the subtask from a plurality of preset operators based on the task information corresponding to each subtask, comprises: Selecting at least one candidate operator capable of executing the subtask from a plurality of preset operators based on task information corresponding to each subtask; Randomly selecting one candidate operator from the at least one candidate operator as a target operator.
  3. 3. The method of claim 1, wherein the resources required by the target operator to execute a process include execution logic of the target operator and memory access resources including at least one of register file partitions, memory address spaces, synchronization primitive resources, communication channel buffers.
  4. 4. The method of claim 3, wherein generating the instruction set corresponding to the subtask according to the resources required by the target operator to execute the process comprises: And combining an instruction corresponding to the execution logic of the target operator with an instruction corresponding to the memory access resource to obtain an instruction set corresponding to the subtask.
  5. 5. The method of claim 1, wherein the task input information includes input data and the task output information includes output data, wherein the analyzing the association between the plurality of subtasks based on the task information of the plurality of subtasks to obtain the association analysis result includes: for each subtask, the following is performed: Traversing all target subtasks by taking the subtasks as reference subtasks, and determining at least one target subtask with the same input data as the output data of the reference subtask, wherein all target subtasks are other subtasks except the reference subtask in the plurality of subtasks; and taking the at least one target subtask as a subtask with an association relation with the reference subtask.
  6. 6. The method of claim 1, wherein the task information of each subtask further includes task level information, and the analyzing the association relationship between the plurality of subtasks according to the task information of the plurality of subtasks, to obtain an association relationship analysis result, includes: And analyzing the association relation among the plurality of subtasks according to the task input information, the task output information and the task level information of the plurality of subtasks to obtain an association relation analysis result.
  7. 7. The method of claim 6, wherein the task input information comprises input data and the task output information comprises output data, wherein analyzing the association between the plurality of subtasks based on the task input information, the task output information, and the task level information for the plurality of subtasks to obtain an association analysis result comprises: for each subtask, the following is performed: Traversing all target subtasks by taking the subtasks as reference subtasks, and determining at least one target subtask with the same input data as the output data of the reference subtask, wherein all target subtasks are all subtasks of a next task level of a task level where the reference subtask is located; and taking the at least one target subtask as a subtask with an association relation with the reference subtask.
  8. 8. The method of claim 6, wherein the task level information for the plurality of subtasks is determined according to the following: Arranging the plurality of subtasks according to a preset arrangement rule, and determining a two-dimensional row matrix of the plurality of subtasks; and carrying out hierarchical division on the plurality of subtasks based on the coordinate information of the plurality of subtasks in the two-dimensional row matrix to obtain task hierarchical information of each subtask.
  9. 9. An instruction generating apparatus, the apparatus comprising: the system comprises an acquisition module, a task verification module and a task output module, wherein the acquisition module is used for acquiring task verification information of a target object, wherein the task verification information comprises task information of a plurality of subtasks of the target task; the analysis module is used for analyzing the association relation among the plurality of subtasks according to the task information of the plurality of subtasks to obtain an association relation analysis result; The system comprises an instruction generation module, an instruction set generation module, a target operator execution module and a control module, wherein the instruction generation module is used for selecting a target operator capable of executing a subtask from a plurality of preset operators based on task information corresponding to each subtask; the instruction generation module is further used for generating a target instruction set based on the instruction sets corresponding to the plurality of subtasks and the association relation analysis result, wherein the instructions in the target instruction set are used for verifying the verification result of the target object on the target task.
  10. 10. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the steps of the instruction generating method according to any of claims 1-8 when the computer program is executed.

Description

Instruction generation method, device, equipment and storage medium Technical Field The present application relates to the field of artificial intelligence chips, and in particular, to a method, an apparatus, a device, and a storage medium for generating instructions. Background The processor Core is a fully concurrent system, such as a GPU Core (graphics processing unit, general purpose processor Core). When applied, programs are typically translated into descriptors and instructions that run on the system. In the chip development stage, no program is usually available, and a chip verifier is required to develop corresponding instructions according to an instruction set to perform system-level chip verification on a processor core. The method mainly uses a manual writing operator to generate a corresponding instruction, and then performs system-level chip verification according to the generated instruction. However, the method is completely dependent on the manual writing progress, so that the verification efficiency is low, and a large amount of manpower resources are wasted. Therefore, how to automatically generate the instruction for chip verification and improve the verification efficiency is a technical problem to be solved in the industry. Disclosure of Invention The embodiment of the application provides a method, a device, equipment and a storage medium for generating instructions for chip verification, which are used for automatically generating the instructions for chip verification and improving verification efficiency. In a first aspect, an embodiment of the present application provides an instruction generating method, including: Task verification information of a target object is obtained, wherein the task verification information comprises task information of a plurality of subtasks of the target task, and the task information of each subtask comprises task input information and task output information; According to the task information of the plurality of subtasks, the association relation among the plurality of subtasks is analyzed, and an association relation analysis result is obtained; Selecting a target operator capable of executing the subtask from a plurality of preset operators based on task information corresponding to each subtask, and generating an instruction set corresponding to the subtask according to resources required by an execution process of the target operator, wherein an instruction in the instruction set is used for simulating the execution process of the subtask by the target operator; And generating a target instruction set based on the instruction sets corresponding to the plurality of subtasks and the association relation analysis result, wherein the instructions in the target instruction set are used for verifying the verification result of the target object on the target task. In some embodiments, the selecting, based on the task information corresponding to each subtask, a target operator capable of executing the subtask from a plurality of preset operators includes: Selecting at least one candidate operator capable of executing the subtask from a plurality of preset operators based on task information corresponding to each subtask; Randomly selecting one candidate operator from the at least one candidate operator as a target operator. In some embodiments, the resources required by the target operator to execute the process include execution logic of the target operator and memory access resources including at least one of register file partitions, memory address spaces, synchronization primitive resources, communication channel buffers. In some embodiments, the generating the instruction set corresponding to the subtask according to the resource required by the target operator to execute the process includes: And combining an instruction corresponding to the execution logic of the target operator with an instruction corresponding to the memory access resource to obtain an instruction set corresponding to the subtask. In some embodiments, the task input information includes input data, the task output information includes output data, and the analyzing the association between the plurality of subtasks according to the task information of the plurality of subtasks to obtain an association analysis result includes: Traversing all target subtasks by taking the subtask as a reference subtask, and determining at least one target subtask with the same input data as the output data of the reference subtask, wherein all target subtasks are other subtasks except the reference subtask in the plurality of subtasks; and taking the at least one target subtask as a subtask with an association relation with the reference subtask. In some embodiments, the task information of each subtask further includes task level information, and the analyzing, according to the task information of the plurality of subtasks, the association relationship between the plurality of subtasks to ob