CN-122021493-A - High-speed serial interface physical IP verification platform, method, equipment and medium

CN122021493ACN 122021493 ACN122021493 ACN 122021493ACN-122021493-A

Abstract

The application relates to the technical field of integrated circuits and provides a verification platform, a method, equipment and a medium for a physical IP of a high-speed serial interface. The application provides a unified design and verification platform supporting coexistence and fusion of multiple protocol types and capable of using multi-protocol physical layer intellectual property cores, which is based on a modularized, parameterized and multi-protocol harmonious coexistence design idea and a top-layer architecture circuit design method, can effectively reduce the circuit design and verification personnel cost of various different protocol types in project development, obviously shortens the function and performance verification period of the physical layer intellectual property cores, obviously improves the development efficiency of a full stack and a full field aiming at architecture design, circuit development and function/performance full-scale verification of different protocol types, improves the multiplexing degree of the design and verification platform among different protocols, and provides an excellent paradigm of the unified design and verification of the platform level.

Inventors

JI DAWEI
CHENG HUALI
Kong Siye
Yin Binjun
WANG LU

Assignees

芯耀辉半导体科技(上海)有限公司

Dates

Publication Date: 20260512
Application Date: 20260129

Claims (20)

1. A verification platform for high-speed serial interface physical IP, the verification platform comprising: A transaction layer for generating a single protocol type stimulus sequence and a multi-protocol type stimulus sequence, wherein the transaction layer comprises a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component; An interface layer for driving the high-speed serial interface multiprotocol type physical interface proxy component and the unified type serial interface proxy component, sampling a stimulus sequence transmitted through the multiprotocol type physical interface itself and received by the multiprotocol type physical interface and transmitted through the unified type serial interface, and sampling a stimulus sequence transmitted through the unified type serial interface itself and received by the unified type serial interface and transmitted through the multiprotocol type physical interface; A signal layer for providing the multi-protocol type physical interface and the unified type serial interface for interfacing with a design to be tested, Wherein the serial port protocol associated with the design under test is a single protocol or a combination of multiple protocols, When the serial port protocol associated with the design to be tested is a single protocol, the verification platform analyzes the highest speed of the interface signal of the design to be tested, generates an excitation sequence of the single protocol type, thereby starting the protocol consistency verification of the single protocol type corresponding to the serial port protocol associated with the design to be tested, When the serial port protocol associated with the design to be tested is a multi-protocol combination, the verification platform determines that the serial port protocol associated with the design to be tested is a combination of a first serial port protocol and a second serial port protocol, then respectively analyzes key parameters of the first serial port protocol and the second serial port protocol, and generates an excitation sequence of the multi-protocol type, so that protocol consistency verification of the multi-protocol type corresponding to the combination of the first serial port protocol and the second serial port protocol is started, and the first serial port protocol is different from the second serial port protocol.
2. The verification platform of claim 1, wherein the serial protocol associated with the design under test is a Serdes protocol, the design under test being one or more Serdes physical layer intellectual property cores conforming to the Serdes protocol.
3. The authentication platform of claim 2, wherein the high-speed serial interface multiprotocol type physical interface proxy component is configured to generate a stimulus sequence of the multiprotocol type transmitted through the multiprotocol type physical interface, the unified type serial interface proxy component is configured to generate a stimulus sequence of the multiprotocol type transmitted through the unified type serial interface, and the interface layer comprises a physical interface transmitting side sampler configured to sample the stimulus sequence transmitted through the multiprotocol type physical interface itself and a physical interface receiving side sampler configured to sample the stimulus sequence transmitted through the unified type serial interface received by the multiprotocol type physical interface, the interface layer further comprises a serial interface transmitting side sampler configured to sample the stimulus sequence transmitted through the unified type serial interface itself and a serial interface receiving side sampler configured to sample the stimulus sequence transmitted through the multiprotocol type physical interface received by the unified type serial interface.
4. A verification platform according to claim 3, wherein the transaction layer further comprises a physical interface receiving side auto-checker for automatically checking the excitation sequence transmitted over the unified type serial interface received by the multiprotocol type physical interface sampled by the physical interface receiving side sampler of the interface layer, and a serial interface transmitting side auto-checker for automatically checking the excitation sequence transmitted over the unified type serial interface itself sampled by the serial interface transmitting side sampler of the interface layer.
5. The authentication platform of claim 4, wherein the interface layer includes a driver component for driving the high-speed serial interface multiprotocol type physical interface proxy component and the unified type serial interface proxy component, and wherein the driver component, the physical interface transmit side sampler, the physical interface receive side sampler, the serial interface transmit side sampler, and the serial interface receive side sampler included in the interface layer are usable for bottom-to-top integration and physical layer multiplexing of system-in-chip.
6. The verification platform of claim 2, wherein the serial protocols associated with the design under test belong to a set of Serdes protocols, the set of Serdes protocols including versions of a high speed serial peripheral interconnect bus protocol, versions of a serial hard disk interface advanced specification protocol, versions of a universal serial bus protocol, versions of a display interface protocol, versions of an ethernet protocol, and versions of a data converter and logic device high speed serial interface protocol.
7. The verification platform of claim 6, wherein when the serial protocols associated with the design under test are single protocols, the serial protocols associated with the design under test are any one of the set of Serdes protocols, and when the serial protocols associated with the design under test are multi-protocol combinations, the combination of the first serial protocol and the second serial protocol is a combination of PCIe protocol and SATA protocol, a combination of PCIe protocol and USB protocol, or a combination of USB protocol and DP protocol.
8. The verification platform of claim 2, wherein the signal layer further comprises an assertion verifier for the multi-protocol type physical interface, the assertion verifier associating a top-level physical interface of the design under test by binding to perform a timing-level assertion verification, wherein the multi-protocol type protocol consistency verification corresponding to the combination of the first serial port protocol and the second serial port protocol comprises the timing-level assertion verification.
9. The verification platform of claim 2, wherein the hierarchy of the verification platform includes the transaction layer, the interface layer, and the signal layer, the hierarchy of the verification platform being determined based on functional differentiation, the transaction layer representing a communication environment of the design under test, the interface layer representing a behavioral level description of a functional module, the signal layer representing transmission of commands and data during communication of the design under test.
10. The verification platform of claim 9, wherein the transaction layer further comprises a behavioral level reference model supporting a physical level register abstraction layer model including a register data structure and a memory data structure, the behavioral level reference model for independently configuring and software read-write access operations to the multiprotocol commonality circuit and the multiprotocol differencing circuit, respectively.
11. The authentication platform of claim 10, wherein the multi-protocol commonality circuit is an intersection between the first serial protocol associated circuit and the second serial protocol associated circuit, and wherein the multi-protocol differencing circuit is a union between the first serial protocol associated circuit and the second serial protocol associated circuit minus an intersection between the first serial protocol associated circuit and the second serial protocol associated circuit.
12. The verification platform of claim 10, wherein when the serial port protocol associated with the design under test is a multi-protocol combination and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 3.0 protocol and USB 3.0 protocol, the multi-protocol commonality circuit comprises a codec circuit, a clock generation circuit, and a phase-locked loop circuit, the multi-protocol differencing circuit comprises a periodic low frequency signal detection circuit and a low power consumption management circuit.
13. The authentication platform of claim 12, wherein the authentication platform utilizes the transaction layer to emulate a control plane based on the PCIe 3.0 protocol for issuing input-output read-write instructions and to emulate a power consumption and power management plane based on the USB 3.0 protocol for providing system-level power and low-power management gears.
14. The verification platform of claim 10, wherein when the serial port protocol associated with the design under test is a combination of multiple protocols and the combination of the first serial port protocol and the second serial port protocol is a combination of PCIe 5.0 protocol and SATA protocol, the multiple protocol commonality circuit comprises a low speed codec circuit, a low power management circuit, and a physical layer calibration and adaptation circuit, the multiple protocol differencing circuit comprises a high speed codec circuit, a high speed receive side channel margin circuit, and a high speed transmit side equalization circuit.
15. The verification platform of claim 14, wherein the verification platform utilizes the transaction layer to simulate a control plane based on the PCIe 5.0 protocol for issuing high-speed low-latency memory read-write instructions and a storage plane based on the SATA protocol for initiating physical-level hard disk low-speed data access and handling operations.
16. A method for verifying physical IP of a high-speed serial interface, the method comprising: Determining whether a serial port protocol associated with the design to be tested is a single protocol or a multi-protocol combination; when the serial port protocol associated with the to-be-tested design is a single protocol, analyzing the highest speed of the interface signal of the to-be-tested design to generate an excitation sequence of a single protocol type, so as to start protocol consistency verification of the single protocol type corresponding to the serial port protocol associated with the to-be-tested design, and be used for designing functional characteristic design, performance design and protocol specification compliance of the to-be-tested design; when the serial port protocol associated with the design to be tested is a multi-protocol combination, determining that the serial port protocol associated with the design to be tested is a combination of a first serial port protocol and a second serial port protocol, then respectively analyzing respective key parameters of the first serial port protocol and the second serial port protocol to generate a multi-protocol type excitation sequence, thereby starting multi-protocol type protocol consistency verification corresponding to the combination of the first serial port protocol and the second serial port protocol, wherein the first serial port protocol is different from the second serial port protocol, Wherein the stimulus sequence of the single protocol type and the stimulus sequence of the multiple protocol type are generated by a transaction layer of a verification platform, the transaction layer comprises a high-speed serial interface multiple protocol type physical interface proxy component and a unified type serial interface proxy component, the verification platform further comprises an interface layer used for driving the high-speed serial interface multiple protocol type physical interface proxy component and the unified type serial interface proxy component, the verification platform further comprises a signal layer used for providing a multiple protocol type physical interface and a unified type serial interface which are in butt joint with the design to be tested, the interface layer is further used for sampling the stimulus sequence which is sent by the multiple protocol type physical interface and received by the multiple protocol type physical interface and sent by the unified type serial interface, and the interface layer is further used for sampling the stimulus sequence which is sent by the unified type serial interface and received by the unified type serial interface and sent by the multiple protocol type physical interface.
17. The method of verification of claim 16, wherein the serial protocol associated with the design under test is a Serdes protocol, the design under test being one or more Serdes physical layer intellectual property cores conforming to the Serdes protocol.
18. The method of claim 17, wherein the hierarchy of verification platforms includes the transaction layer, the interface layer, and the signal layer, the hierarchy of verification platforms being determined based on functional differentiation, the transaction layer representing a communication environment of the design under test, the interface layer representing a behavioral level description of a functional module, the signal layer representing transmission of commands and data during communication of the design under test.
19. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, the processor implementing the method according to any one of claims 16 to 18 when the computer program is executed.
20. A computer readable storage medium storing computer instructions which, when run on a computer device, cause the computer device to perform the method of any one of claims 16 to 18.

Description

High-speed serial interface physical IP verification platform, method, equipment and medium Technical Field The present application relates to the field of integrated circuit technologies, and in particular, to a platform, a method, an apparatus, and a medium for verifying a physical IP of a high-speed serial interface. Background In the fields of high-speed digital communication, high-speed interfaces, etc., serialization/deserialization (Serdes) is widely used, sometimes also referred to as Serdes. Some communication protocols and interface standards use high-speed Serdes serial interfaces, such as the high-speed serial peripheral interconnect bus protocol (PCI Express, PCIe), the serial hard disk interface advanced Specification protocol (SERIAL ADVANCED Technology Attachment, SATA), the universal high-speed serial bus protocol (Universal Serial Bus, USB), the Display Port (DP), the Ethernet protocol (ETH), and the data converter and logic device high-speed serial interface protocol (JESD). These different types of Serdes protocols are each continuously iterating and evolving, and the product morphology and application scenarios of physical layer intellectual property cores (PHY IPs) developed based on these Serdes protocols are also more abundant and diverse, thus presenting challenges to chip design and verification. From top-level architecture planning to circuit design to interface function and performance verification, consideration needs to be given to how to provide extensibility and compatibility for different protocol types, such as constructing different excitation sequence patterns for different protocol types, modeling and automatic verification of protocol-related registers, and the like. The chip verification scheme in the prior art generally provides verification in the design development process only for a single protocol type or two single protocol types, and requires that a predetermined number of protocols have docking requirements, and that corresponding network interfaces be reserved or corresponding protocol ports be supported by means of configuration replacement. For example, chinese patent application publication No. CN102929756a discloses a bus development verification platform that maintains a low-speed bus interface for compatibility with a low-speed bus, and also maintains a high-speed serial bus interface, such as a high-speed serial SATA storage interface, for development verification of a storage bus SATA. For another example, chinese patent with application publication No. CN118540248a discloses that by updating the protocol port configuration of the protocol conversion chip, the transceiver delay of the Serdes interface of multiple protocols is measured, for example, configured as a PCIe protocol port or configured as an ethernet protocol port. However, the chip verification scheme supporting multi-protocol verification in the prior art lacks overall optimization from the top-level design, is difficult to adapt to new protocol types or new versions, also needs to occupy additional hardware resources to reserve interfaces, or needs to increase delay to switch configuration among protocol ports, is unfavorable for reducing the cost and time of overall project design development and verification, is difficult to match with various high-speed serial Serdes protocols which are continuously updated and evolved at present, and is difficult to meet the requirements of rapid iteration and verification of high-speed SERDES PHY IP products. Therefore, the application provides a high-speed serial interface physical IP verification platform, a method, equipment and a medium, which are used for solving the technical problems in the prior art. Disclosure of Invention In a first aspect, the present application provides a high-speed serial interface physical IP verification platform. The verification platform comprises a transaction layer, an interface layer and a signal layer, wherein the transaction layer is used for generating a single protocol type excitation sequence and a multi-protocol type excitation sequence, the transaction layer comprises a high-speed serial interface multi-protocol type physical interface proxy component and a unified type serial interface proxy component, the interface layer is used for driving the high-speed serial interface multi-protocol type physical interface proxy component and the unified type serial interface proxy component, sampling the excitation sequence sent through the multi-protocol type physical interface and received by the multi-protocol type physical interface and sent through the unified type serial interface, and sampling the excitation sequence sent through the unified type serial interface and received by the unified type serial interface and sent through the multi-protocol type physical interface, and the signal layer is used for providing the multi-protocol type physical interface and the unified type serial interface which are in bu