CN-122021494-A - Verification platform for PCIe6

CN122021494ACN 122021494 ACN122021494 ACN 122021494ACN-122021494-A

Abstract

The application relates to the technical field of integrated circuits and provides a verification platform for PCIe 6. The verification platform of the physical layer intellectual property core under the general PCIe bus protocol specification is provided, the highest transmission rate and the maximum transmission bandwidth supported by the PCIe6 protocol can be adapted, the customization requirements from interface bandwidth, clock mode and working mode to physical interface version, which are proposed by rapid iterative development, are adapted, the object-oriented expandability and the support for multiple modes and polymorphism are provided, the loss of a special directional verification platform which is required to be redeveloped after each adjustment of the chip design or verification scheme is avoided, the update cost of early-stage development and middle-later-stage iterative maintenance of a project is reduced, the labor investment of the whole project is saved, and the chip development period of the whole project is shortened.

Inventors

JI DAWEI
Kong Siye
CHENG HUALI

Assignees

芯耀辉半导体科技(上海)有限公司

Dates

Publication Date: 20260512
Application Date: 20260129

Claims (14)

1. An authentication platform for PCIe6, the authentication platform comprising: A transaction layer for generating a parameterized stimulus sequence conforming to PCIe protocol specifications, wherein the transaction layer includes a multi-mode PCIe6 physical interface proxy component and a PCIe6 serial interface proxy component; An interface layer for driving the PCIe6 physical interface proxy component and the PCIe6 serial interface proxy component, sampling excitation sequences sent through the PCIe6 physical interface itself and received by the PCIe6 physical interface and sent through the PCIe6 serial interface, and sampling excitation sequences sent through the PCIe6 serial interface itself and received by the PCIe6 serial interface and sent through the PCIe6 physical interface; A signal layer for providing the PCIe6 physical interface and the PCIe6 serial interface for interfacing with a design under test, The verification platform is used for multiple verifications of PCIe6 protocols of the design to be tested, the verification platform provides a parameterized configuration interface, the configuration interface is used for setting bus bit width, interface version, clock mode, working mode and initialization acceleration mode or non-acceleration mode of the PCIe6 physical interface, and the multiple verifications of the PCIe6 protocols of the design to be tested comprise function verification, performance verification, observability debugging verification and protocol consistency verification for measuring protocol compliance.
2. The verification platform of claim 1, wherein the design under test is one or more PCIe6 physical layer intellectual property cores compliant with PCIe 6.0 or higher order versions.
3. The verification platform of claim 1, wherein the design under test is one or more PCIe6 physical layer intellectual property cores that are downward compatible with lower-order versions including PCIe1.0, PCIe2.0, PCIe3.0, PCIe4.0, and PCIe5.0.
4. The verification platform of claim 2, wherein the PCIe6 physical interface proxy component is configured to generate a stimulus sequence sent over the PCIe6 physical interface, the PCIe6 serial interface proxy component is configured to generate a stimulus sequence sent over the PCIe6 serial interface, and the interface layer includes a physical interface send side sampler configured to sample the stimulus sequence sent over the PCIe6 physical interface itself and a physical interface receive side sampler configured to sample the stimulus sequence sent over the PCIe6 serial interface received by the PCIe6 physical interface, the interface layer further includes a serial interface send side sampler configured to sample the stimulus sequence sent over the PCIe6 serial interface itself and a serial interface receive side sampler configured to sample the stimulus sequence sent over the PCIe6 physical interface received by the PCIe6 serial interface.
5. The verification platform of claim 4, wherein the transaction layer further comprises a physical interface receive side auto-checker for automatically checking a sequence of stimuli received by the PCIe6 physical interface and sent over the PCIe6 serial interface sampled by the physical interface receive side sampler of the interface layer, and a serial interface send side auto-checker for automatically checking a sequence of stimuli sampled by the serial interface send side sampler of the interface layer and sent over the PCIe6 serial interface itself.
6. The verification platform of claim 5, wherein the interface layer includes a driver component for driving the PCIe6 physical interface proxy component and the PCIe6 serial interface proxy component, and wherein the driver component, the physical interface transmit side sampler, the physical interface receive side sampler, the serial interface transmit side sampler, and the serial interface receive side sampler included by the interface layer are available for system-on-chip integration and multiplexing.
7. The verification platform of claim 2, wherein the signal layer further comprises an assertion verifier for the PCIe6 physical interface, the assertion verifier to associate a top-level physical interface of the design under test by a binding manner to perform a sequential level assertion verification, wherein protocol consistency verification among multiple verifications of a PCIe6 protocol of the design under test comprises the sequential level assertion verification.
8. The verification platform of claim 2, wherein the hierarchy of the verification platform includes the transaction layer, the interface layer, and the signal layer, the hierarchy of the verification platform being determined based on functional differentiation, the transaction layer representing a communication environment of the design under test, the interface layer representing a behavioral level description of a functional module, the signal layer representing transmission of commands and data during communication of the design under test.
9. The verification platform of claim 8, wherein the transaction layer further comprises a behavioral level reference model that supports a general verification methodology register abstraction layer model for full register scan testing, interrupt count prediction and lookup, and debug count prediction and lookup, wherein the full register scan testing is for different attributes and different types of configurations and states.
10. The verification platform of claim 8, wherein the signal layer supports the design under test to set a real physical layer design mode and a physical layer model mode, wherein a behavioral level simulation model of the design under test is used to simulate interfacing requirements of the design under test with the PCIe6 physical interface and the PCIe6 serial interface when the design under test is in the physical layer model mode, and wherein the design under test includes a physical coding sublayer, a physical layer soft logic processing unit, and a physical layer hard logic processing unit when the design under test is in the real physical layer design mode.
11. The verification platform of claim 10, wherein the design under test setting the real physical layer design pattern or the physical layer model pattern is determined based on a register transfer level code development completion of the design under test.
12. The verification platform of claim 2, wherein the configuration interface to set the bus bit width, the interface version, the clock mode, the operating mode, the initialization acceleration mode, or the non-acceleration mode of the PCIe6 physical interface comprises the configuration interface to set the bus bit width of the PCIe6 physical interface to be the physical interface bus bit width at a typical rate from PCIe Gen1 to PCIe Gen6, and the configuration interface to set the operating mode of the PCIe6 physical interface to be a native PIPE operating mode or SERDES PIPE operating mode.
13. The verification platform of claim 2, wherein the verification platform supports randomized design, multi-scenario combination testing, functional coverage automation metrics and quantification testing, and random constraint driven based verification.
14. The verification platform of claim 2, wherein the verification platform is used for functional verification, performance verification, observability debugging verification, and protocol consistency verification for measuring protocol compliance of a physical layer intellectual property core of a four-level pulse amplitude modulated PCIe6 protocol of the design to be tested.

Description

Verification platform for PCIe6 Technical Field The application relates to the technical field of integrated circuits, in particular to a verification platform for PCIe 6. Background With the development of technical fields such as artificial intelligence, internet of vehicles, data centers, cloud services and the like, and with the upgrade of high-speed serial peripheral interconnect bus (PCI Express, PCIe) bus protocols and physical interface (PHY INTERFACE for the PCIe, PIPE) interface standards for the high-speed serial peripheral interconnect bus, new transmission signal modulation and coding modes are applied, the highest transmission rate and the maximum transmission bandwidth supported by the bus are also improved, and the changes also present new challenges for the development and verification of PCIe physical layer intellectual property (PHY IP). For example, subsystem development and verification at the PIPE level of PCIe6 protocol requires consideration of IP functionality verification completeness and standardized protocol verification, and also requires consideration of roles in different development stages from register transfer level (REGISTER TRANSFERRING LEVEL, RTL) verification, gate level netlist verification, to silicon verification, etc. The PCIe verification platform in the prior art relies on hardware description language and independent development function of users, has single and directional excitation mode, can only provide relatively simple inspection, lacks object-oriented expandability and support for multiple modes and polymorphism, is difficult to match with continuous updating and evolution PCIe protocol specifications, and also is difficult to meet the requirements of rapid iterative development and verification of corresponding physical layer intellectual property core products. Therefore, the application provides an authentication platform for PCIe6, which is used for solving the technical problems in the prior art. Disclosure of Invention In a first aspect, the present application provides an authentication platform for PCIe 6. The verification platform comprises a transaction layer, an interface layer and a signal layer, wherein the transaction layer is used for generating a parameterized excitation sequence conforming to PCIe protocol specifications, the transaction layer comprises a multimode PCIe6 physical interface proxy component and a PCIe6 serial interface proxy component, the interface layer is used for driving the PCIe6 physical interface proxy component and the PCIe6 serial interface proxy component, sampling the excitation sequence sent through a PCIe6 physical interface and received by the PCIe6 physical interface and sent through the PCIe6 serial interface, and sampling the excitation sequence sent through the PCIe6 physical interface and received by the PCIe6 serial interface and sent through the PCIe6 physical interface, and the signal layer is used for providing the PCIe6 physical interface and the PCIe6 serial interface which are in butt joint with a design to be tested. The verification platform is used for multiple verifications of PCIe6 protocols of the design to be tested, the verification platform provides a parameterized configuration interface, the configuration interface is used for setting bus bit width, interface version, clock mode, working mode and initialization acceleration mode or non-acceleration mode of the PCIe6 physical interface, and the multiple verifications of the PCIe6 protocols of the design to be tested comprise function verification, performance verification, observability debugging verification and protocol consistency verification for measuring protocol compliance. According to the application, a verification platform of a physical layer intellectual property core under a common PCIe bus protocol specification is provided, the highest transmission rate and the highest transmission bandwidth supported by a PCIe6 protocol can be adapted, the customization requirements from interface bandwidth, clock mode and working mode to physical interface version can be adapted for rapid iteration development, the requirements of rapid development and verification of corresponding physical layer intellectual property core products are met by providing an optimally designed layered structure and modularized core components, reference functions are distinguished, such that the platform can be planned from the aspects of environment requirement representation, functional module operation, command and data transmission and the like, object-oriented expandability and support for multiple modes and polymorphism can be provided, the configuration interface and parameterization and polymorphic design can be combined, rich excitation sequences are supported, customizable integrated verification requirements and multiple mode selection combinations are supported, continuous updating and evolution protocol specification are matched, the requirements