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CN-122021496-A - Distributed networking verification method and system

CN122021496ACN 122021496 ACN122021496 ACN 122021496ACN-122021496-A

Abstract

The invention belongs to the field of chip verification and relates to a distributed networking verification method and system, wherein the method is based on the existing single-machine UVM verification environment, a verification assembly is modified through a SystemVerilog DPI mechanism, a network communication interface is added, the split verification environment is respectively deployed on a plurality of interconnected simulation hosts, a cross-simulation host interaction channel is established by using a layered communication architecture, real-time transmission and receiving of interface data are realized, and a bridging assembly based on DPI enables service logic of the single-machine UVM verification environment to be not modified and can be adapted to distributed simulation. The invention supports parallel simulation of multiple simulation hosts, reduces the resource consumption of a single machine, can quickly build a distributed verification environment, can also advance the post-chip-silicon cluster test to an EDA simulation stage, greatly shortens the simulation period, timely discovers the deep logic defects of the chip, and reduces the risk of chip flow.

Inventors

  • ZHANG WANLI
  • BAI CHAOGANG

Assignees

  • 北京数渡信息科技有限公司

Dates

Publication Date
20260512
Application Date
20260409

Claims (12)

  1. 1. The distributed networking verification method is characterized by comprising the following steps of: Step 1, providing a single-machine UVM verification environment for a DUT, wherein the single-machine UVM verification environment comprises a plurality of verification components for performing data interaction with the DUT and an information transmission interface between the verification components and the DUT; Step 2, splitting the single machine UVM verification environment into at least two sub verification environments according to networking verification requirements of the DUT, and respectively deploying the sub verification environments in different simulation hosts capable of network communication; Step 3, aiming at verification components needing to interact across simulation hosts in different sub-verification environments, a network communication interface is called by a DPI mechanism of SystemVerilog to reconstruct an original verification component, so that the reconstructed verification component can realize excitation transmission and data reception across the simulation hosts; Step 4, establishing a cross-simulation host interaction channel between simulation hosts based on a layered communication architecture, wherein the layered communication architecture decouples interaction between multiple verification environments from underlying physical transmission; And 5, synchronously starting simulation processes of all simulation hosts, and realizing real-time data interaction by each sub-verification environment through a cross-simulation host interaction channel to complete distributed networking verification of the DUT.
  2. 2. The method of claim 1, wherein the sub-verification environment in step 2 is a duplicate version of the original single-machine UVM verification environment, and only verification components interacted across simulation hosts are subjected to targeted modification, and the remaining components maintain original functions.
  3. 3. The method of claim 1, wherein the modified verification component in step 3 is transparent to service logic of an original single machine UVM verification environment, and local signal processing logic of the original verification component is not modified and local processing of cross-machine data is realized only by the DPI bridging component.
  4. 4. A distributed networking verification method according to claim 3, wherein the sub-verification environment comprises a DUT and a cascade interface component connected with the DUT; the cascade interface component on at least one simulation host invokes a network communication interface through a SystemVerilog DPI mechanism and is configured to send output data of a local DUT to another simulation host through a network; The cascade interface component on at least one other emulated host invokes the network communication interface through SystemVerilog DPI mechanisms configured to receive data from the other emulated host over the network and drive it as stimulus to the native DUT.
  5. 5. The method of claim 1, wherein in step 4, the underlying physical transmission medium comprises a TCP/IP socket, a shared memory, or a semaphore.
  6. 6. The method of claim 1, wherein the network communication interface is a Socket api, and the modified verification component realizes the bidirectional transmission of excitation and data among different simulation hosts through the Socket api.
  7. 7. The method of claim 1, wherein the hierarchical communication architecture supports both distributed deployment across physical simulation hosts and multi-process parallel deployment within the same simulation host.
  8. 8. The method for verifying distributed networking according to any one of claims 1-7, wherein the DUT is a switch, the switch comprises USP and DSP, a verification component connected with a port is vip, and the vip needing to be interacted with a cross-simulation host is transformed into vip supporting Socket api through a DPI mechanism, so that port data interaction among different switch DUTs is realized.
  9. 9. The method for verifying distributed networking according to any one of claims 1-7, wherein when chip cluster scene verification is required, sub-verification environments corresponding to each DUT are deployed on different simulation hosts respectively, socket api communication function modules are added for each sub-verification environment, a distributed cluster verification environment is built, and chip cluster networking test in an EDA simulation stage is achieved.
  10. 10. The method of claim 1, wherein the DUT is a digital chip module with a cascading interface comprising a switch chip, a processor chip, or a bus bridge chip.
  11. 11. A distributed networking verification system is used for executing the distributed networking verification method disclosed in claim 1 and is characterized by comprising at least two simulation hosts, sub-verification environments deployed in the simulation hosts, a cross-simulation host interaction channel and a DPI bridging component, wherein the sub-verification environments are obtained by splitting and copying a single UVM (ultra-violet machine) verification environment, the DPI bridging component is used for transforming the verification components and realizing local processing of cross-machine data, and the cross-simulation host interaction channel is established based on a layered communication architecture to realize real-time data transmission among the simulation hosts.
  12. 12. A computer readable storage medium having stored thereon a computer program, which when executed by a processor implements a distributed networking authentication method according to any of claims 1 to 10.

Description

Distributed networking verification method and system Technical Field The invention relates to a distributed networking verification method and system, and belongs to the technical field of chip verification. Background The existing digital chip verification method mainly utilizes a UVM environment to develop a matched verification environment for the DUT, namely various components which interact with the DUT, then starts different excitation sources, applies excitation of various scenes to the DUT, simulates the DUT, checks the state of the DUT in the simulation process, judges whether the DUT meets expectations or not, and further finds out design bug inside the DUT. Before this verification process begins, the DUT needs to be compiled with the verification environment using a simulation compilation tool such as VCS/XRUN/MODELSIM, etc., to produce a binary executable. The file is then executed for simulation testing. However, the prior art has a plurality of defects: 1) One test case must only run on one machine, if the hardware resources of the machine are insufficient, such as memory and CPU resources are tense, the simulation time is prolonged, and under serious tense, the simulation process is suspended, so that the simulation test cannot be completed. 2) Complex DUT networking verification cannot be realized, even simple networking verification can greatly increase the resource consumption of a single machine, further prolong the simulation time and cannot reproduce the cluster working scene of the chip; 3) And the verification of a simple networking scene requires the reconstruction of a verification environment, so that the compiling and simulation time is further prolonged. In the related patent literature, the method and the device for managing the multi-chip link in the multi-chip verification environment disclosed by the publication No. CN120822474A can only run on a single machine, the upper limit of single-machine resources is not broken through, the method and the device cannot be realized when the simulation scale of the chip is excessive to a certain extent, and the information transmission between DUTs needs to be forwarded by a third party, so that the interaction efficiency is low. The disclosure number CN120909741a provides a "multithreading-based DPI task processing method, electronic device and medium" for improving simulation efficiency. However, the method is based on a multithreading mode, the mode can only be operated on a single machine, and the verification for the multichip network is also a traditional single machine verification mode. Based on this, the present invention has been proposed. Disclosure of Invention The invention provides a distributed networking verification method and system, and the specific technical scheme is as follows: In a first aspect, a distributed networking verification method is applied to UVM simulation verification of a digital chip, and includes the following steps: Step 1, providing a single-machine UVM verification environment for a DUT, wherein the single-machine UVM verification environment comprises a plurality of verification components for performing data interaction with the DUT and an information transmission interface between the verification components and the DUT; Step 2, splitting the single machine UVM verification environment into at least two sub verification environments according to networking verification requirements of the DUT, and respectively deploying the sub verification environments in different simulation hosts capable of network communication; Step 3, aiming at verification components needing to interact across simulation hosts in different sub-verification environments, a network communication interface is called by a DPI mechanism of SystemVerilog to reconstruct an original verification component, so that the reconstructed verification component can realize excitation transmission and data reception across the simulation hosts; Step 4, establishing a cross-simulation host interaction channel between simulation hosts based on a layered communication architecture, wherein the layered communication architecture decouples interaction between multiple verification environments from underlying physical transmission; And 5, synchronously starting simulation processes of all simulation hosts, and realizing real-time data interaction by each sub-verification environment through a cross-simulation host interaction channel to complete distributed networking verification of the DUT. The method comprises the steps of synchronously starting simulation processes of all simulation hosts, and synchronously starting an implementation mechanism: For example, the emulation commands on each emulation host may be invoked remotely at the same time by an external script, or the emulation may be initiated simultaneously after all processes are guaranteed to be ready by handshaking signals between the emulation hosts. In a further improvemen