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CN-122021497-A - Universal verification platform, method and device for functional module, electronic equipment and medium

CN122021497ACN 122021497 ACN122021497 ACN 122021497ACN-122021497-A

Abstract

The invention discloses a general verification platform, method, device, electronic equipment and medium of a functional module, wherein the platform comprises an excitation signal input module, a verification module and a verification module, wherein the excitation signal input module is used for generating transaction excitation and transmitting the transaction excitation to a reference model and a tested device; the system comprises a reference model, a tested device, an output signal detection module, a score board and a score board, wherein the reference model is used for transmitting transaction excitation to an algorithm model function and sending expected signals to the score board, the tested device is used for generating actual output signals and transmitting the actual output signals to the output signal detection module, the output signal detection module is used for detecting the actual output signals and transmitting the actual output signals to the score board, and the score board is used for verifying the functions of the tested device. The reference model in the platform is connected with the UVM environment through the connection mechanism of the DPI, the algorithm model generates expected data and transmits the data into the verification environment through the DPI interface to detect the correctness of the output of the tested device, the process of compiling the algorithm according to different test cases is omitted, the rapid verification of the complex algorithm is realized, the development difficulty of the universal verification platform is reduced, and the verification efficiency is improved.

Inventors

  • LI HUAYU
  • LUO LICHUAN
  • LI XIANGJUN
  • SU GUOBIN
  • ZHAO SHUANGMEI
  • LIU DIJUN

Assignees

  • 宸芯科技股份有限公司

Dates

Publication Date
20260512
Application Date
20241112

Claims (18)

  1. 1. The universal verification platform based on the universal verification methodology UVM environment is characterized by comprising a register configuration module, an excitation signal input module, a reference model, a device to be tested, an output signal detection module and a score board; The register configuration module, the excitation signal input module and the output signal detection module are respectively used for being connected with a tested device connected to the general verification platform, the reference model is respectively connected with the excitation signal input module and the score board, the score board is also connected with the output signal detection module, the reference model comprises a DPI, a target file is imported into the DPI, the target file comprises an algorithm model function based on C language, and the algorithm model function is used for realizing processing logic inside the tested device, wherein: the register configuration module is used for carrying out parameter configuration on at least one register in the tested device according to the test case input into the UVM environment; The excitation signal input module is used for generating transaction excitation matched with the test case and transmitting the transaction excitation to the reference model and the tested device; The system comprises a reference model, a score board and a database, wherein the reference model is used for transmitting received transaction excitation to a pre-imported algorithm model function through DPI and transmitting an expected signal generated by the algorithm model function for the transaction excitation to the score board; The device under test is used for responding to the transaction excitation, generating an actual output signal matched with the transaction excitation through internally defined processing logic, and transmitting the actual output signal to the output signal detection module; The output signal detection module is used for transmitting the detected actual output signal sent by the device to be detected to the score board; And the score board is used for carrying out function verification on the tested device according to the received actual output signal and the expected signal.
  2. 2. The universal verification platform according to claim 1, wherein the tested device comprises a plurality of end-to-end functional sub-modules, every two adjacent functional sub-modules form a sub-module pair, and the universal verification platform further comprises a process real-time detection assembly, wherein the process real-time detection assembly is respectively connected with the output end of a previous functional sub-module in at least one sub-module pair and a reference model; the reference model is further used for transmitting expected output sub-values of each functional sub-module of the tested device to a process real-time detection component for printing in the process of generating an actual output signal matched with the transaction excitation through internally defined processing logic, and generating a matched printing file; the process real-time detection component is specifically used for comparing the actual output sub-value with the matched expected output sub-value in the printing file when the actual output sub-value is acquired from the target function sub-module of the tested device, printing the error position when the comparison error is detected, and ending the continuous test of the tested device when the detected comparison error exceeds the preset quantity threshold value.
  3. 3. The universal verification platform according to claim 2, wherein the device under test is embodied as a universal digital front-end processing algorithm module; The general digital front-end processing algorithm module comprises a time domain frequency offset calibration sub-module and a low-pass filtering sub-module, and the process real-time detection assembly is respectively connected with the output ends of the time domain frequency offset calibration sub-module and the low-pass filtering sub-module.
  4. 4. A generic verification platform according to any one of claims 1-3, wherein the register configuration module comprises in particular a register model, an adapter and a verification intellectual property core VIP for acting as a bus, connected in sequence; the register model is used for modeling each register contained in the tested device according to the test case to obtain register configuration parameters, and transmitting the register configuration parameters to the adapter; and the adapter is used for converting the received register configuration parameters into a data format which is matched with the VIP, and transmitting the data format to the tested device through the VIP so as to carry out parameter configuration on at least one register in the tested device.
  5. 5. The universal authentication platform of claim 4, wherein the VIP is configured to act as an advanced high performance bus based on an on-chip bus protocol.
  6. 6. A generic verification platform according to any one of claims 1-3, wherein the stimulus signal input module comprises in particular a stimulus generator, a driver and a monitor; a stimulus generator for generating a transaction stimulus matching the test case; The driver is used for sequentially sending the transaction stimulus to the tested equipment according to a preset time sequence requirement; and the monitor is used for transmitting the detected transaction stimulus to the reference model when the transaction stimulus is detected.
  7. 7. A generic verification platform according to any one of claims 1-3, further comprising a top layer configuration module; The top layer configuration module is used for configuring basic parameters of the reference model, the register configuration module, the excitation signal input module and the score board before testing the tested device.
  8. 8. A universal verification platform according to any one of claims 1 to 3 wherein data transmission is performed between the excitation signal input module and the reference model via a first in first out queue and data transmission is performed between the output signal detection module and the scoreboard via a first in first out queue.
  9. 9. A generic verification platform according to any one of claims 1-3, wherein said object file is implemented by adding a layer of shell functions outside the algorithmic model functions, the number, type, input or output direction of interface parameters defined in the shell functions being determined by the functions implemented by the device under test and the configuration parameters required by the UVM environment.
  10. 10. A universal verification platform according to any one of claims 1-3, wherein the test cases are entered in the form of at least one seed number, each seed number pointing to a set test file, and wherein the test files are automatically executed in batches in the form of an automated script based on the respective seed numbers.
  11. 11. A universal verification method based on UVM environment, performed by a reference model in a universal verification platform according to any of claims 1-3, the method comprising: the transaction excitation generated and sent by the excitation signal input module is acquired and transmitted to a pre-imported algorithm model function through DPI; And sending expected signals generated by the algorithm model function for transaction excitation to a score board.
  12. 12. The universal validation method of claim 11, wherein the method further comprises: generating, by the internally defined processing logic, an actual output signal that matches the transaction stimulus; and printing expected output sub-values of each functional sub-module of the tested device, generating a matched printing file and transmitting the matched printing file to the process real-time detection component.
  13. 13. A universal verification method based on UVM environment, performed by a process real-time detection component in a universal verification platform according to any of claims 2-3, the method comprising: acquiring an actual output sub-value at a target function sub-module of a tested device; and comparing the actual output sub-value with the matched expected output sub-value in the print file, and ending the continuous test of the tested device when the detected comparison error exceeds a preset quantity threshold value.
  14. 14. A universal verification device based on UVM environment, characterized by a reference model configured in the universal verification platform according to any of claims 1-3, the device comprising: The transaction excitation acquisition module is used for acquiring the transaction excitation generated and transmitted by the excitation signal input module; a transaction incentive transmission module for transmitting the transaction incentive to a pre-imported algorithm model function through DPI; and the expected signal sending module is used for sending expected signals generated by the algorithm model function aiming at the business excitation to the score board.
  15. 15. A universal verification device based on UVM environment, characterized by a process real-time detection component configured in the universal verification platform according to any of claims 2-3, the device comprising: The actual output sub-value acquisition module is used for acquiring the actual output sub-value at the target function sub-module of the tested device; And the output sub-value comparison module is used for comparing the actual output sub-value with the matched expected output sub-value in the print file, and ending the continuous test of the tested device when the detected comparison error exceeds the preset quantity threshold value.
  16. 16. An electronic device, the electronic device comprising: at least one processor, and A memory communicatively coupled to the at least one processor, wherein, The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the UVM environment based universal authentication method of any of claims 11-13.
  17. 17. A computer readable storage medium storing computer instructions for causing a processor to implement the universal UVM environment based authentication method of any of claims 11-13 when executed.
  18. 18. A computer program product, characterized in that the computer program product comprises a computer program which, when executed by a processor, implements a universal authentication method based on a UVM environment according to any of claims 11-13.

Description

Universal verification platform, method and device for functional module, electronic equipment and medium Technical Field The present invention relates to the field of functional verification technologies of chip algorithm modules, and in particular, to a general verification platform, method, apparatus, electronic device, medium, and program product for a functional module. Background With the increasing complexity of integrated circuit designs, the importance of verification work is becoming increasingly prominent, and common verification methodologies (Universal Verification Methodology, UVM) are commonly used in the industry to build efficient, reusable verification platforms by providing standardized frameworks and components. In the prior art, conventional UVM-based verification platforms require the same functionality of complex algorithms, such as digital front end (Digital Front End, DFE) processing algorithms, to obtain the desired output of the design under test (Design under Test, DUT). For the complex algorithm module of DFE, the verifier needs to reproduce the complex algorithm in the verification platform, which requires high labor cost and time cost, is error-prone, and has high risk. The traditional verification scheme and technology can only realize black box verification, and if errors occur, the design and verification personnel also need higher labor cost and time cost for positioning the errors. Disclosure of Invention The invention provides a general verification platform, method, device, electronic equipment, medium and program product of a functional module, which are used for solving the problems of low verification efficiency, high platform development difficulty, low positioning error accuracy and low efficiency of complex algorithm. According to one aspect of the embodiment of the invention, a universal verification platform based on a universal verification methodology UVM environment is provided, comprising a register configuration module, an excitation signal input module, a reference model, a tested device, an output signal detection module and a score board; the system comprises a register configuration module, an excitation signal input module and an output signal detection module, wherein the register configuration module, the excitation signal input module and the output signal detection module are respectively connected with a tested device connected to a universal verification platform, a reference model is respectively connected with the excitation signal input module and the score board, the score board is also connected with the output signal detection module, a DPI (Direct Programming Interface ) is contained in the reference model, a target file is imported in the DPI, a C-language-based algorithm model function is contained in the target file, the algorithm model function is used for realizing processing logic inside the tested device, the register configuration module is used for carrying out parameter configuration on at least one register in the tested device according to a test case input to a UVM environment, the excitation signal input module is used for generating transaction excitation matched with the test case and transmitting the transaction excitation to the reference model and the tested device, the reference model is used for transmitting the received transaction excitation to the algorithm model function imported in advance and transmitting a desired signal generated by the algorithm model function to the score board, the tested device is used for responding to the transaction excitation, the transaction excitation logic is defined in an internal, the transaction excitation is generated by the transaction excitation logic is used for generating a real signal and transmitting the transaction excitation signal to the real signal matched with the real signal to the tested device, the real signal is transmitted to the real signal to the tested device, and the function verification module is used for performing function verification on the tested device according to the received actual output signal and the expected signal. According to another aspect of the embodiment of the invention, a universal verification method based on a UVM environment is provided, and the universal verification method is executed by a reference model in a universal verification platform and comprises the steps of acquiring transaction stimulus generated and sent by a stimulus signal input module, transmitting the transaction stimulus to a pre-imported algorithm model function through a DPI, and sending a desired signal generated by the algorithm model function for the transaction stimulus to a score board. According to another aspect of the embodiment of the invention, a universal verification method based on a UVM environment is provided, and the universal verification method is executed by a process real-time detection component in a universal verification platform, and comp