CN-122021498-A - Synchronous verification method for asynchronous interrupt event

CN122021498ACN 122021498 ACN122021498 ACN 122021498ACN-122021498-A

Abstract

The invention provides a synchronous verification method for asynchronous interrupt events, which comprises the steps of constructing a system-level verification platform designed by a general processor with synchronous instruction level based on a UVM verification methodology, loading an excitation binary file to enable the system-level verification platform to work normally so as to realize synchronous instruction level verification, creating asynchronous interrupt event excitation which comprises the triggering time of the asynchronous interrupt event, injecting the asynchronous interrupt event into a product to be tested through a UVM environment frame in the normal working process of the system-level verification platform, and injecting the asynchronous interrupt event into a reference model when the asynchronous interrupt event is detected to occur, so that the reference model synchronously triggers the same asynchronous interrupt event, and realizing synchronous instruction level verification when the asynchronous interrupt event occurs. The synchronous verification method for the asynchronous interrupt event enables the synchronous relation of instruction submission to be established between the product to be tested and the reference model, and synchronous verification can be carried out for the asynchronous interrupt event.

Inventors

XIAO LONG
DU XIAOJING
WANG HENGYU
WANG TAN
QIN BIAO

Assignees

中国科学院上海高等研究院

Dates

Publication Date: 20260512
Application Date: 20241112

Claims (10)

1. A synchronous verification method for asynchronous interrupt events, comprising: Step S1, a system-level verification platform designed by a general processor for instruction-level synchronization is built based on a UVM verification methodology, and an excitation binary file is loaded to enable the binary file to work normally so as to realize instruction-level synchronization verification; Step S2, creating asynchronous interrupt event excitation, wherein the asynchronous interrupt event excitation at least comprises asynchronous interrupt event triggering time taking a clock of a product to be tested as a unit; And step S3, injecting an asynchronous interrupt event into the product to be tested through a UVM environment framework according to the excitation of the asynchronous interrupt event in the normal working process of the system-level verification platform, injecting the asynchronous interrupt event into a reference model when the asynchronous interrupt event of the product to be tested is detected, enabling the reference model to synchronously trigger the same asynchronous interrupt event, and then enabling the system-level verification platform to continue to normally work so as to realize instruction-level synchronous verification when the asynchronous interrupt event occurs.
2. The method of claim 1, wherein the system level verification platform of the general purpose processor design comprises a product to be tested, a UVM environment framework, and a reference model for simulating an instruction level processor, the reference model comprising a reference model memory module and a reference model cache queue; The step S1 specifically comprises the step S12 of loading the same excitation binary file to a memory module of the product to be tested and a pointing start address of a designated processor in a reference model memory module, and then starting the product to be tested to lead the product to be tested to point out, decode, execute and submit an instruction from the memory module of the product to be tested; the step S3 includes the step S31 of analyzing the asynchronous interrupt excitation file by the UVM environment framework, caching each analyzed asynchronous interrupt event excitation into a UVM cache queue according to the ascending order of the triggering time of the asynchronous interrupt event, and simultaneously analyzing the asynchronous interrupt excitation file by the reference model, and caching the analyzed asynchronous interrupt event excitation into the reference model cache queue according to the ascending order of the triggering time of the asynchronous interrupt event.
3. The method of claim 2, wherein in step S2 the asynchronous interrupt event stimulus corresponds to an interrupt exception handling subroutine, and in step S1 the binary code of the interrupt exception handling subroutine is loaded simultaneously with the loading of the stimulus binary.
4. The method according to claim 2, wherein step S1 further comprises, prior to step S12, performing step S11 of establishing a request channel and a response channel of one-way blocking between a process of the UVM environment frame and a process of the reference model of the architecture level simulation; after the step S12, a step S13 is executed, wherein the UVM environment framework monitors the instruction submitting behavior of the product to be tested, and sends a request data packet data_req of an instruction submitting event to the reference model through a request channel when one instruction submitting is detected, and simultaneously transmits the data to be compared from the product to be tested to the scoreboard; step S14, the scoreboard performs comparison verification on the to-be-compared data from the product to be tested and the to-be-compared data from the reference model; And S15, after the UVM environment framework acquires a response data packet data_rsp submitted by the reference model instruction from the response channel, the product to be tested takes the instruction from the memory module of the product to be tested, decodes, executes and submits the next instruction, and returns to the step S13 until the last instruction of the excitation binary file takes the instruction and the comparison verification is completed.
5. The method of claim 4, wherein step S13 further comprises the UVM environment frame blocking the progress of the UVM environment frame until the response data packet data_rsp of the reference model instruction commit is obtained from the response channel after detecting one instruction commit, and the reference model blocking the progress of the reference model after transmitting the response data packet data_rsp of the reference model instruction commit until the request data packet data_req of the instruction commit event is received from the request channel.
6. The method according to claim 4, wherein in the step S14, if the comparison data from the product to be tested and the comparison data from the reference model are identical, the comparison verification is passed, and the step S5 is executed, otherwise, the comparison fails, the verification flow is terminated and the verification is judged not to be passed.
7. The method according to claim 2, wherein the step S3 further comprises: step S32, in the normal working process of the product to be tested, detecting asynchronous interrupt event excitation of the head of a UVM buffer queue in each simulation clock period by a UVM environment frame, and driving the asynchronous interrupt event excitation to the product to be tested when the triggering time of the asynchronous interrupt event preset by the asynchronous interrupt event excitation is reached; Step S33, when the UVM environmental framework detects that an asynchronous interrupt event of a product to be tested occurs, a request data packet data_req of the asynchronous interrupt event is sent to a reference model; Step S34, the reference model receives a request data packet data_req of an asynchronous interrupt event, reads an excitation of the asynchronous interrupt event from a cache queue of the reference model and triggers a corresponding asynchronous interrupt event; Step S35, the system-level verification platform continues to work normally to enable the product to be tested and the reference model to execute the interrupt processing subprogram so as to perform instruction synchronous verification on the interrupt processing subprogram until a complete interrupt subprogram instruction is executed; And step S36, repeating the step S32 to the step S35 to verify all instructions in the excitation binary file.
8. The method according to claim 7, wherein in the step S33, when the detected asynchronous interrupt event of the product to be tested occurs that the instruction corresponding to the repeated string operation prefix is interrupted, the request packet data_req of the asynchronous interrupt event carries a count value of the number of times of execution of the loop remaining when the instruction is interrupted; in the step S34, if the request packet data_req of the asynchronous interrupt event carries a count value of the number of times of execution remaining in the cycle when the instruction is interrupted, the reference model executes the instruction until the cycle count value reaches the count value of the number of times of execution remaining in the cycle or after the zero flag bit condition is satisfied, then triggers the corresponding asynchronous interrupt event.
9. The method of claim 7, wherein step S33 further comprises, upon occurrence of an asynchronous interrupt event for the product under test, prior to sending the request packet data_req for the asynchronous interrupt event, the product under test performing field protection and jumping the instruction pointer to the entry of the interrupt handling subroutine, and subsequently blocking the progress of the product under test until the UVM environment framework obtains the response packet data_rsp submitted by the reference model instruction from the reference model via the response channel.
10. The method of claim 7, wherein the asynchronous interrupt event stimulus further comprises other interrupt event related information such as interrupt vector number, interrupt target processor index, interrupt mode, and interrupt type.

Description

Synchronous verification method for asynchronous interrupt event Technical Field The invention belongs to the technical field of chip verification, and particularly relates to a synchronous verification method aiming at an asynchronous interrupt event. Background With the rapid growth of the design scale of integrated circuits, efficient and complete verification means are becoming more important to ensure design reliability. UVM (unified verification methodology) is a currently mainstream general verification platform development framework, provides a rich class library based on SystemVerilog language, and can be widely used in the industry by utilizing reusable components thereof to construct a functional simulation verification environment with a standardized hierarchical structure and interfaces and improve the expansibility and the collaboration of large verification projects. In the UVM framework, the reference model (REFERENCE MODEL) is a necessary independent module that mimics the same function and behavior of RTL (Register-TRANSFER LEVEL, register transfer level) designs in a highly abstract manner. In IC verification, the reference model is used as an ideal model for comparing with an RTL (Register-TRANSFER LEVEL, register transfer level) simulation platform to judge whether the RTL simulation platform operates correctly or not. For system-level functional verification requirements of general-purpose processors, architecture-level functional simulators are typically employed as verification reference models under the UVM (unified verification methodology) framework. Although the system lacks enough micro-architecture information and clock precision and cannot keep a synchronous relation with an RTL (Register-TRANSFER LEVEL, register transfer stage) simulation platform on a clock, the system can be used for comparing and verifying an instruction submitting sequence, an architecture Register state, an instruction triggered synchronous event sequence and the simulation platform under a certain condition. Therefore, on the premise that the reference model and the simulation platform establish an asynchronous execution relationship, comparison verification is carried out on the architecture state after instruction execution, and the method becomes a common method for verifying the system-level front-end function of the general processor chip. Asynchronous interrupt events are caused by electrical signals generated by the timer of the CPU or by an external device such as an IO device, and can change the instruction execution sequence of the CPU, except the time point when the asynchronous interrupt events occur is unexpected. Because the random characteristic of the asynchronous interrupt event does not have a sequence relation with the execution of the CPU instruction, and the RTL simulation platform and the reference model cannot be synchronous in clock in the asynchronous verification environment, the RTL simulation platform and the reference model cannot trigger the interrupt under the premise of the same architecture state, and therefore the effectiveness and completeness of verification of the asynchronous interrupt event and the processing subprogram thereof are lost. Disclosure of Invention The invention aims to provide a synchronous verification method for an asynchronous interrupt event, so that a synchronous relation of instruction submission is established between a product to be tested and a reference model, and synchronous verification can be carried out for the asynchronous interrupt event. In order to achieve the above object, the present invention provides a synchronous verification method for asynchronous interrupt event, including: s1, constructing a system-level verification platform designed by a general processor for instruction-level synchronization based on a UVM verification methodology, and loading an excitation binary file to enable the binary file to work normally so as to realize instruction-level synchronization verification; s2, creating asynchronous interrupt event excitation, and caching to obtain an asynchronous interrupt excitation file, wherein the asynchronous interrupt event excitation at least comprises asynchronous interrupt event triggering time which takes a clock of a product to be tested as a unit; And S3, injecting an asynchronous interrupt event into the product to be tested through a UVM environment framework according to the excitation of the asynchronous interrupt event in the normal working process of the system-level verification platform, injecting the asynchronous interrupt event into a reference model when the asynchronous interrupt event of the product to be tested is detected, enabling the reference model to synchronously trigger the same asynchronous interrupt event, and then enabling the system-level verification platform to continue to normally work so as to realize instruction-level synchronous verification when the asynchronous interrupt even