CN-122021499-A - Verification method and device for monitoring correctness of high-performance processor in real time

CN122021499ACN 122021499 ACN122021499 ACN 122021499ACN-122021499-A

Abstract

A method for verifying correctness of high-performance processor includes fetching instruction submitting information, control state register information, fixed point register information, floating point register information, vector register information and interrupt information when target instruction is executed by tested meter, analyzing instruction submitting information to obtain structured data packet of target instruction, extracting target instruction information and corresponding executing context information from structured data packet of target instruction, inputting to reference model to make reference model simulate execution of target instruction to obtain reference result of target instruction, comparing first updated value of register in reference result with corresponding register information in structured data packet to obtain correctness verification result of tested meter. The method can carry out real-time monitoring and state comparison on various key registers in the CPU architecture, and effectively avoids loopholes missing caused by incomplete register monitoring.

Inventors

LU JUN
LIN SIBO
WU DEZHI
JI LI

Assignees

成都群芯微电子科技有限公司

Dates

Publication Date: 20260512
Application Date: 20251223

Claims (10)

1. A method of verifying the correctness of a high performance processor in real time, the method comprising: Capturing instruction submitting information, control state register information, fixed point register information, floating point register information, vector register information and interrupt information when a tested design executes a target instruction; analyzing the instruction submitting information, the control state register information, the fixed point register information, the floating point register information, the vector register information and the interrupt information to obtain a structured data packet of the target instruction; Extracting target instruction information and corresponding execution context information from a structured data packet of the target instruction, and inputting the target instruction information and the corresponding execution context information into a reference model so that the reference model simulates the execution of the target instruction to obtain a reference result of the target instruction, wherein the reference result at least comprises a first register update value; And comparing the first updated value of the register in the reference result with corresponding register information in the structured data packet to obtain a correctness verification result of the tested design.
2. The method of claim 1, wherein fetching instruction commit information, control state register information, fixed point register information, floating point register information, vector register information, and interrupt information when the design under test executes the target instruction further comprises: Reorganizing the register files accessed by the sub banks in the tested design to form a continuous logical view of register entries for access; the updating of a register renaming relation table in the tested design is monitored in real time, and the mapping relation among a fixed-point register, a floating-point register, a vector register and respective physical registers is updated according to the updated register renaming relation table; Collecting instruction submitting information and interrupt information in the tested design; collecting control state register information in the tested design; and accessing the reorganized register file based on the mapping relation to respectively acquire the fixed-point register information, the floating-point register information and the vector register information.
3. The method according to claim 2, wherein the method further comprises: monitoring a pipeline stage of the target instruction in the tested design, and generating a data acquisition synchronous trigger signal aiming at the target instruction when the target instruction reaches a specified pipeline stage; And responding to the data acquisition synchronous trigger signal, executing the steps of acquiring instruction submitting information and interrupt information in the tested design, acquiring control state register information in the tested design, accessing the recombined register file based on the mapping relation, and respectively acquiring the fixed point register information, floating point register information and vector register information.
4. A method according to claim 3, wherein the pipeline stages comprise an instruction rename stage, an instruction issue stage, an instruction execute stage and an instruction commit stage.
5. The method according to claim 1, wherein the method further comprises: Determining whether the target instruction is interrupted in the tested design according to the interruption information; if yes, inputting the interrupt information into the reference model so as to enable the reference model to execute interrupt to obtain an interrupt execution result, wherein the interrupt execution result at least comprises a second updated value of a register; And comparing the second updated value of the register in the interrupt execution result with corresponding register information in the structured data packet to obtain a correctness verification result of the tested design.
6. The method of claim 5, wherein the interrupt information comprises interrupt response information, interrupt handling information, or clear interrupt information.
7. A verification device for monitoring correctness of a high-performance processor in real time is characterized by comprising a monitor, a scoreboard and a reference model; The monitor is used for capturing instruction submitting information, control state register information, fixed point register information, floating point register information, vector register information and interrupt information when the tested design executes a target instruction; the monitor comprises a data packer, a data processing unit and a control unit, wherein the data packer is used for analyzing the instruction submitting information, the control state register information, the fixed point register information, the floating point register information, the vector register information and the interrupt information to obtain a structured data packet of the target instruction; The scoreboard is used for extracting target instruction information and corresponding execution context information from a structured data packet of the target instruction, inputting the target instruction information and the corresponding execution context information into the reference model so that the reference model simulates the execution of the target instruction to obtain a reference result of the target instruction, wherein the reference result at least comprises a first register update value, and comparing the first register update value in the reference result with corresponding register information in the structured data packet to obtain a correctness verification result of the tested design.
8. The apparatus of claim 7, wherein the monitor comprises a register file reorganizer, a rename map tracker, a control flow tracker, a status register monitor, a fixed point register value acquirer, a floating point register value acquirer, and a vector register value acquirer; The register file reorganizer is used for reorganizing the register files accessed by the partition bank in the tested design to form a continuous logical view of the register entries for access; the renaming mapping tracker is used for monitoring updating of a register renaming relation table in the tested design in real time, and updating mapping relations among a fixed-point register, a floating-point register, a vector register and respective physical registers according to the updated register renaming relation table; the control flow tracker is used for collecting instruction submitting information and interrupt information in the tested design; The state register monitor is used for collecting control state register information in the tested design; The fixed point register value acquirer is used for accessing the register file after reorganization based on the mapping relation to acquire the fixed point register information; The floating point register value acquirer is used for accessing the reorganized register file based on the mapping relation to acquire the floating point register information; The vector register value acquirer is used for accessing the register file after reorganization based on the mapping relation to acquire the vector register information.
9. The apparatus of claim 8, wherein the monitor further comprises a pipeline signal synchronizer; The pipeline signal synchronizer is used for monitoring a pipeline stage of the target instruction in the tested design and generating a data acquisition synchronous trigger signal aiming at the target instruction when the target instruction reaches a specified pipeline stage; The fixed point register value acquirer, the floating point register value acquirer and the vector register value acquirer are further used for responding to the data acquisition synchronous trigger signal, accessing the reorganized register file based on the mapping relation and respectively acquiring the fixed point register information, the floating point register information and the vector register information.
10. The apparatus of claim 7, wherein the scoreboard is further configured to determine whether the target instruction is interrupted in the design under test based on the interrupt information; if yes, inputting the interrupt information into the reference model so as to enable the reference model to execute interrupt to obtain an interrupt execution result, wherein the interrupt execution result at least comprises a second updated value of a register; And comparing the second updated value of the register in the interrupt execution result with corresponding register information in the structured data packet to obtain a correctness verification result of the tested design.

Description

Verification method and device for monitoring correctness of high-performance processor in real time Technical Field The embodiment of the specification relates to the technical field of computers, in particular to a verification method and device for monitoring correctness of a high-performance processor in real time. Background With the continuous progress of integrated circuit technology, the number of transistors that can be integrated in a unit area is continuously rising, and the design complexity of a high-performance CPU is also greatly increased because mainstream CPU chips can accommodate billions to billions of transistors. In order to improve the instruction level parallelism (IPC), modern high-performance CPUs widely adopt a superscalar architecture, and introduce complex technologies such as branch prediction, out-of-order execution, multi-level caching, synchronous multithreading, multi-core and the like, which brings unprecedented challenges to function verification work. Verification of asynchronous interrupt handling by high performance processors is also a great difficulty, and the verification platform must be able to properly communicate interrupt information and ensure consistency of interrupt behavior between the reference model and the Design Under Test (DUT). Meanwhile, in the multi-core CPU, memory consistency further increases the establishment difficulty of the verification environment. When the behaviors of the DUT and the reference model are inconsistent, the verification platform also needs to have real-time error reporting capability so as to help the verification personnel to quickly locate the problem and avoid the waste of computing resources. In the existing processor correctness verification method, only the comparison of general registers is supported, which results in insufficient verification coverage of the full functional state of the CPU and difficulty in finding hidden deep errors. Therefore, how to verify the full-function status of the processor is a technical problem to be solved. Disclosure of Invention In order to solve the problems in the prior art, the embodiment of the specification provides a verification method and a device for monitoring the correctness of a high-performance processor in real time, and the verification of the full-function state of the processor is realized. The specific technical scheme of the embodiment of the specification is as follows: In one aspect, embodiments of the present disclosure provide a method for verifying the correctness of a high-performance processor in real time, where the method includes: Capturing instruction submitting information, control state register information, fixed point register information, floating point register information, vector register information and interrupt information when a tested design executes a target instruction; analyzing the instruction submitting information, the control state register information, the fixed point register information, the floating point register information, the vector register information and the interrupt information to obtain a structured data packet of the target instruction; Extracting target instruction information and corresponding execution context information from a structured data packet of the target instruction, and inputting the target instruction information and the corresponding execution context information into a reference model so that the reference model simulates the execution of the target instruction to obtain a reference result of the target instruction, wherein the reference result at least comprises a first register update value; And comparing the first updated value of the register in the reference result with corresponding register information in the structured data packet to obtain a correctness verification result of the tested design. Further, capturing instruction commit information, control state register information, fixed point register information, floating point register information, vector register information, and interrupt information when the tested device executes the target instruction further includes: Reorganizing the register files accessed by the sub banks in the tested design to form a continuous logical view of register entries for access; the updating of a register renaming relation table in the tested design is monitored in real time, and the mapping relation among a fixed-point register, a floating-point register, a vector register and respective physical registers is updated according to the updated register renaming relation table; Collecting instruction submitting information and interrupt information in the tested design; collecting control state register information in the tested design; and accessing the reorganized register file based on the mapping relation to respectively acquire the fixed-point register information, the floating-point register information and the vector register information. Further, the