CN-122021501-A - Processor debugging method, device, equipment and computer readable storage medium

CN122021501ACN 122021501 ACN122021501 ACN 122021501ACN-122021501-A

Abstract

The invention discloses a processor debugging method, device, equipment and a computer readable storage medium, which are applied to the technical field of computers and comprise the steps of collecting full-dimension state information of instructions in the execution process of pipelines of each stage of a processor in a full-flow process in a prototype verification stage of the processor, uploading program counter values of the instructions and the full-dimension state information to an upper computer, determining the instructions and original data according to the program counter values, performing pure software simulation execution on the instructions by using a proprietary instruction simulator of the upper computer based on the original data, generating instruction execution reference data matched with the full-dimension state information collection dimension, comparing the instruction execution reference data with the full-dimension state information in an instruction level full-dimension mode, positioning fault sources in the verification of the processor, and determining a debugging result. The problem of fault coupling location is difficult is solved, and the debugging efficiency and the accuracy of processing prototype verification are improved.

Inventors

WEI HONGYANG
ZOU XIAOFENG
ZHANG ZHENLEI

Assignees

山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date: 20260512
Application Date: 20260130

Claims (10)

1. A method for debugging a processor, comprising: In a prototype verification stage of a processor, acquiring full-dimension state information of an instruction in the pipeline execution process of each stage of the processor in a full-flow manner, and uploading a program counter value of the instruction and the full-dimension state information to an upper computer; Determining the instruction and the original data according to the program counter value, performing pure software simulation execution on the instruction by using a dedicated instruction simulator of the upper computer based on the original data, and generating instruction execution reference data matched with the full-dimension state information acquisition dimension; And carrying out instruction-level full-dimension comparison on the instruction execution reference data and the full-dimension state information, positioning a fault source in the verification of the processor, and determining a debugging result.
2. The processor debugging method of claim 1, wherein, in a prototype verification stage of a processor, collecting full-dimensional state information of an instruction in a pipeline execution process of each stage of the processor, and uploading a program counter value of the instruction and the full-dimensional state information to an upper computer, comprising: The method comprises a prototype verification stage of the processor, a full-flow acquisition stage, a full-dimensional state information acquisition stage and a full-dimensional state information acquisition stage, wherein the full-dimensional state information of the instruction is acquired in the execution process of each stage of pipeline of the processor, and the pipeline comprises a value-taking stage, a decoding stage, a transmitting stage, an executing stage, a writing-back stage and a retirement stage; Storing the full-dimensional state information into an information cache region, and updating the full-dimensional state information of the instruction in the information cache region to an information storage module after the instruction enters the retirement stage of a pipeline and the execution is completed and a retirement completion signal is validated; And uploading all full-dimensional state information of the instruction in the information storage module and a program counter value of the instruction to the upper computer through a data interface.
3. The processor debugging method of claim 2, further comprising: and when the instruction has the operation of clearing the buffer area in the execution process of each stage of pipeline of the processor, clearing the full-dimension state information of the unfinished instruction temporarily stored in the information buffer area.
4. The processor debugging method of claim 2, further comprising: And monitoring the storage state of the information buffer area in real time, and outputting pipeline pause signals when the information buffer area is full, so that each stage of pipeline of the processor is paused, and releasing the pipeline pause signals after the information buffer area has a spare space, and resuming execution of each stage of pipeline of the processor.
5. The processor debugging method of claim 1, wherein determining the instruction and the original data according to the program counter value, and performing pure software simulation execution on the instruction by using a dedicated instruction simulator of the upper computer based on the original data, generating instruction execution reference data matched with the full-dimension state information acquisition dimension, comprises: Generating an address according to the program counter value, and calling the corresponding instruction from an instruction storage module of the exclusive instruction simulator according to the address, and calling the corresponding original data from a data storage module of the exclusive instruction simulator; Based on the original data and the instruction, performing pure software simulation execution by using the exclusive instruction simulator, and generating instruction execution reference data matched with the full-dimension state information acquisition dimension.
6. The processor debugging method of claim 1, wherein comparing the instruction execution reference data and the full-dimensional state information in instruction level full-dimension, locating a root of a fault in the processor verification, determining a debugging result, comprises: Comparing the instruction information in the instruction execution reference data with the instruction information in the full-dimension state information, and judging that the instruction information is abnormal if the comparison is inconsistent; and comparing the execution result data in the instruction execution reference data with the result data in the full-dimension state information, and judging that the execution result is abnormal if the comparison is inconsistent.
7. The processor debugging method of claim 1, further comprising: The corresponding original data is called from a data storage module of the exclusive instruction simulator, and the original source data is read from a data storage of the prototype; and comparing the original data with the original source data, and judging that the source data is abnormal if the comparison is inconsistent.
8. A processor debugging device, comprising: The pipeline execution module is used for collecting the full-dimension state information of the instruction in the pipeline execution process of each stage of the processor in the prototype verification stage of the processor, and uploading the program counter value of the instruction and the full-dimension state information to the upper computer; The software simulation module is used for determining the instruction and the original data according to the program counter value, performing pure software simulation execution on the instruction by using a dedicated instruction simulator of the upper computer based on the original data, and generating instruction execution reference data matched with the full-dimension state information acquisition dimension; And the comparison module is used for carrying out instruction-level full-dimension comparison on the instruction execution reference data and the full-dimension state information, positioning a fault source in the verification of the processor and determining a debugging result.
9. A processor debugging device, comprising: A memory for storing a computer program; a processor for implementing the processor debugging method according to any one of claims 1 to 7 when executing the computer program.
10. A computer readable storage medium having stored therein computer executable instructions which when loaded and executed by a processor implement the processor debugging method of any of claims 1 to 7.

Description

Processor debugging method, device, equipment and computer readable storage medium Technical Field The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a computer readable storage medium for debugging a processor. Background In the prior art, the RISC-V (reduced instruction set computer) official debug/trace standard scheme has long development period and complex realization, is specially designed for debugging finished chips after streaming, has strong invasiveness and cannot be rapidly deployed in a prototype verification stage, and the conventional debugging means adopted in the prototype verification stage have the problems of limited storage capacity, incomplete debugging data and delayed analysis, cannot effectively distinguish fault sources, seriously affects the development and verification efficiency of a RISC-V processor, and restricts the full play of customization advantages. Therefore, a debugging scheme which is suitable for a prototype verification stage of a processor, is low in invasiveness and efficient and accurate in fault location is needed, and the technical problems of low debugging efficiency and difficult fault location at present are solved. Disclosure of Invention Accordingly, the present invention is directed to a method, apparatus, device and computer readable storage medium for debugging a processor, which solve the problems of low debugging efficiency and difficult fault location in the prior art. In order to solve the technical problems, the present invention provides a processor debugging method, including: In a prototype verification stage of a processor, acquiring full-dimension state information of an instruction in the pipeline execution process of each stage of the processor in a full-flow manner, and uploading a program counter value of the instruction and the full-dimension state information to an upper computer; Determining the instruction and the original data according to the program counter value, performing pure software simulation execution on the instruction by using a dedicated instruction simulator of the upper computer based on the original data, and generating instruction execution reference data matched with the full-dimension state information acquisition dimension; And carrying out instruction-level full-dimension comparison on the instruction execution reference data and the full-dimension state information, positioning a fault source in the verification of the processor, and determining a debugging result. In one aspect, in a prototype verification stage of a processor, collecting full-dimension state information of an instruction in a pipeline execution process of each stage of the processor in a full-flow manner, and uploading a program counter value of the instruction and the full-dimension state information to an upper computer, wherein the method comprises the following steps: The method comprises a prototype verification stage of the processor, a full-flow acquisition stage, a full-dimensional state information acquisition stage and a full-dimensional state information acquisition stage, wherein the full-dimensional state information of the instruction is acquired in the execution process of each stage of pipeline of the processor, and the pipeline comprises a value-taking stage, a decoding stage, a transmitting stage, an executing stage, a writing-back stage and a retirement stage; Storing the full-dimensional state information into an information cache region, and updating the full-dimensional state information of the instruction in the information cache region to an information storage module after the instruction enters the retirement stage of a pipeline and the execution is completed and a retirement completion signal is validated; And uploading all full-dimensional state information of the instruction in the information storage module and a program counter value of the instruction to the upper computer through a data interface. In one aspect, the method further comprises: and when the instruction has the operation of clearing the buffer area in the execution process of each stage of pipeline of the processor, clearing the full-dimension state information of the unfinished instruction temporarily stored in the information buffer area. In one aspect, the method further comprises: And monitoring the storage state of the information buffer area in real time, and outputting pipeline pause signals when the information buffer area is full, so that each stage of pipeline of the processor is paused, and releasing the pipeline pause signals after the information buffer area has a spare space, and resuming execution of each stage of pipeline of the processor. On the one hand, the instruction and the original data are determined according to the program counter value, and based on the original data, the instruction is simulated and executed by pure software by using a dedicated