CN-122021504-A - Nuclear bus parameterization design method and device, electronic equipment and storage medium

CN122021504ACN 122021504 ACN122021504 ACN 122021504ACN-122021504-A

Abstract

The disclosure provides a nuclear bus parameterization design method and device, electronic equipment and storage medium, and relates to the technical field of digital processor design. The method comprises the steps of analyzing and obtaining the corresponding relation between the client interface and the internal unified interface by reading a data file containing interface description and function channel configuration, and automatically generating a corresponding logic structure according to the starting state and attribute parameters of the function sub-module, so that the adaptation logic can be generated based on interface mapping, and a comprehensive bus circuit description file can be generated by combining the configuration parameters, thereby realizing the integrated generation of interface adaptation, function cutting and structure construction. The technical scheme can maintain flexible configurability of the bus structure when meeting different project demands, can reduce repeated labor brought by manual coding, can reduce design risk caused by inconsistent modification, and can improve development efficiency and maintainability of the bus.

Inventors

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Assignees

摩尔线程智能科技(北京)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20251216

Claims (13)

1. A method for parameterizing an in-core bus, comprising: Receiving an input bus instance configuration file, wherein the bus instance configuration file comprises interface description of a client interface connected with a target custom bus and configuration parameter information of a function sub-module of each function channel in the target custom bus; Analyzing the bus instance configuration file according to a target reading mode, obtaining an interface mapping relation between the client interface and an internal general interface based on the interface description, and obtaining an enabling state of the function sub-module and an attribute parameter value thereof based on the configuration parameter information; generating interface conversion logic data based on the interface mapping relation, wherein the interface conversion logic data is used for realizing conversion from the client interface to the internal general interface; And generating a hardware circuit description file based on the starting state of the functional sub-module, the attribute parameter value thereof and the interface conversion logic data, wherein the hardware circuit description file is used for instantiating and constructing a hardware circuit for obtaining the target custom bus.
2. The method of claim 1, wherein prior to receiving the input bus instance profile, the method further comprises: constructing a general interface structure body of a structure body type as the internal general interface according to a set of all operation types of the client access bus; the universal interface structure body comprises a plurality of basic interface combinations, and the basic interface combinations are used for replacing and realizing the functions of the client interfaces corresponding to the operation types.
3. The method according to claim 2, wherein deriving an interface mapping between the client interface and an internal generic interface based on the interface description comprises: Determining the current operation type supported by the client interface according to the description of the client interface in the bus instance configuration file; and based on the current operation type, matching is carried out in a general interface structure body of the internal general interface, a basic interface combination corresponding to the current operation type is determined, and the basic interface combination is used as the interface mapping relation.
4. A method according to any one of claims 1 to 3, wherein generating interface conversion logic data based on the interface mapping relationship comprises: And inputting the interface mapping relation into an interface conversion script to generate the interface conversion logic data for converting the client interface into the internal general interface.
5. The method of claim 1, wherein generating the hardware circuit description file based on the enabled state of the functional sub-module and the attribute parameter values thereof and the interface conversion logic data comprises: Generating initial hardware description data of the function sub-module corresponding to each function channel according to the starting state of the function sub-module by utilizing a condition generation statement of a hardware description language; performing parameter adjustment on the initial hardware description code through the attribute parameter value of the functional sub-module to obtain target hardware description data of the started functional sub-module; and integrating the generated interface conversion logic data with the target hardware description data to form the hardware circuit description file.
6. The method according to claim 5, wherein the generating the initial hardware description data of the function sub-module corresponding to each of the function channels according to the enabled state of the function sub-module by using the conditional generation statement of the hardware description language includes: Generating initial hardware description data of the functional sub-module when the current enabling state of the functional sub-module is determined to be enabled, and/or When it is determined that the enabled state of the current functional sub-module is disabled, initial hardware description data is generated that bypasses the circuit bypass logic of the functional sub-module.
7. The method of claim 5, wherein the functional channels comprise one or more of an instruction channel, a write data channel, and a read data channel, and the bus instance profile comprises a read data channel enable flag and a write data channel enable flag; The generating, by using a conditional generation statement of a hardware description language, initial hardware description data of a function sub-module corresponding to each function channel according to an enabling state of the function sub-module, including: When the enabling mark of the read data channel indicates that the read data channel is enabled, generating first hardware description data of a function sub-module corresponding to the read data channel according to the enabling state of the function sub-module corresponding to the read data channel by utilizing a conditional generation statement of a hardware description language, and/or When the enabling mark of the write data channel indicates that the write data channel is enabled, generating second hardware description data of the function sub-module corresponding to the write data channel according to the enabling state of the function sub-module corresponding to the write data channel by utilizing a conditional generation statement of a hardware description language, and Generating third hardware description data of the functional sub-module corresponding to the instruction channel according to the starting state of the functional sub-module corresponding to the instruction channel by utilizing a conditional generation statement of a hardware description language; And generating initial hardware description data of the function sub-module corresponding to each function channel through the first hardware description data and/or the second hardware description data and the third hardware description data.
8. The method of claim 7, wherein the functional submodules of the instruction channel include at least an arbitration logic submodule, a superdistribution constraint submodule, an access address alignment submodule, a priority control submodule and a cache synchronization broadcast submodule; the function sub-module of the write data channel at least comprises a write data sequence control sub-module, a data cache sub-module and a write data bandwidth conversion sub-module; The function sub-module of the read data channel at least comprises a read data bandwidth conversion sub-module, a data sequence detection sub-module, a data cache sub-module, a data rearrangement sub-module and a bypass detection sub-module.
9. The method of claim 5, wherein the bus instance configuration file includes timing optimization configuration parameters; And performing parameter adjustment on the initial hardware description code through the attribute parameter value of the functional sub-module to obtain target hardware description data of the started functional sub-module, wherein the method comprises the following steps: And carrying out parameter adjustment on the initial hardware description code through the attribute parameter value of the functional sub-module, and carrying out long-path time sequence optimization on the initial hardware description code after parameter adjustment according to the time sequence optimization configuration parameter to obtain target hardware description data of the started functional sub-module.
10. The method of claim 1, wherein parsing the bus instance profile in a read-target manner comprises: Analyzing the bus instance configuration file into two-dimensional dictionary data; And circularly traversing the two-dimensional dictionary data, and extracting the description information of the client interface and the configuration parameter information of the functional sub-module.
11. An in-core bus parameterization design apparatus, comprising: The system comprises a configuration file reading module, a configuration file processing module and a configuration file processing module, wherein the configuration file reading module is used for receiving an input bus instance configuration file, and the bus instance configuration file comprises interface descriptions of client interfaces connected with a target custom bus and configuration parameter information of function sub-modules of all function channels in the target custom bus; The configuration file analysis module is used for analyzing the bus instance configuration file according to a target reading mode, obtaining an interface mapping relation between the client interface and an internal general interface based on the interface description, and obtaining an enabling state of the function sub-module and an attribute parameter value thereof based on the configuration parameter information; The interface conversion module is used for generating interface conversion logic data based on the interface mapping relation, and the interface conversion logic data is used for realizing conversion from the client interface to the internal general interface; And the hardware circuit description module is used for generating a hardware circuit description file based on the starting state of the functional sub-module, the attribute parameter value thereof and the interface conversion logic data, and the hardware circuit description file is used for instantiating and constructing a hardware circuit for obtaining the target custom bus.
12. An electronic device, comprising: Processor, and A memory having stored thereon computer readable instructions which when executed by the processor implement the method of parameterizing an in-core bus as defined in any one of claims 1 to 10.
13. A computer-readable storage medium, on which a computer program is stored, which computer program, when being executed by a processor, implements the method of parameterizing an in-core bus as claimed in any one of claims 1 to 10.

Description

Nuclear bus parameterization design method and device, electronic equipment and storage medium Technical Field The disclosure relates to the technical field of digital processor design, in particular to a method and a device for parameterizing an in-core bus, electronic equipment and a storage medium. Background In the field of integrated circuit design, a core internal bus needs to balance efficient data transfer with design flexibility. At present, the conventional customized design scheme can realize targeted efficiency and area optimization, but the design process is highly dependent on manpower, a large amount of repeated hardware description code writing and modifying work is needed whenever the client interface or function requirement of bus connection changes, so that the development efficiency is low and the maintenance is difficult, on the other hand, the general bus protocol scheme can improve the standardization degree of the design, but the application scene is relatively fixed, and the redundant protocol overhead brings unnecessary area loss and performance compromise, so that the optimal power efficiency is difficult to realize. Therefore, how to effectively improve the automation level of the design and reduce the development and maintenance costs while maintaining the advantages of high efficiency and flexibility of the customization scheme is a problem to be solved at present. It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art. Disclosure of Invention An object of the embodiments of the present disclosure is to provide a method for parameterizing an in-core bus, an apparatus for parameterizing an in-core bus, an electronic device, and a computer readable storage medium, so as to reduce repetitive labor caused by manual coding, reduce design risk caused by inconsistent modification, and improve development efficiency and maintainability of the bus. Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure. According to a first aspect of an embodiment of the present disclosure, there is provided a method for designing a parameterization of an in-core bus, including: Receiving an input bus instance configuration file, wherein the bus instance configuration file comprises interface description of a client interface connected with a target custom bus and configuration parameter information of a function sub-module of each function channel in the target custom bus; Analyzing the bus instance configuration file according to a target reading mode, obtaining an interface mapping relation between the client interface and an internal general interface based on the interface description, and obtaining an enabling state of the function sub-module and an attribute parameter value thereof based on the configuration parameter information; generating interface conversion logic data based on the interface mapping relation, wherein the interface conversion logic data is used for realizing conversion from the client interface to the internal general interface; And generating a hardware circuit description file based on the starting state of the functional sub-module, the attribute parameter value thereof and the interface conversion logic data, wherein the hardware circuit description file is used for instantiating and constructing a hardware circuit for obtaining the target custom bus. In some example embodiments of the present disclosure, based on the foregoing, before receiving the input bus instance profile, the method further comprises: constructing a general interface structure body of a structure body type as the internal general interface according to a set of all operation types of the client access bus; the universal interface structure body comprises a plurality of basic interface combinations, and the basic interface combinations are used for replacing and realizing the functions of the client interfaces corresponding to the operation types. In some example embodiments of the present disclosure, based on the foregoing solution, obtaining, based on the interface description, an interface mapping relationship between the client interface and an internal generic interface includes: Determining the current operation type supported by the client interface according to the description of the client interface in the bus instance configuration file; and based on the current operation type, matching is carried out in a general interface structure body of the internal general interface, a basic interface combination corresponding to the current operation type is determined, and the basic interface combination is used as the interface mapping relation. In some example embodim