CN-122021505-A - Data transmission circuit, chip, data transmission method, medium, and program product

Abstract

The present application relates to a data transmission circuit, a chip, a data transmission method, a medium, and a program product. The data transmission circuit comprises a first-stage trigger used for outputting data to a second-stage trigger module under the control of clock signals output by a clock source, the second-stage trigger module comprises N+1 second triggers, the update period of output data of each second trigger is N+1 clock periods of the clock source, the triggered clock periods of each second trigger are different, N+1 is a natural number greater than or equal to 1, the third-stage trigger module comprises a data selector and a third trigger which are connected, the data selector is used for selecting one path from multiple paths of data output by the second-stage trigger module in each clock period of the clock source, and outputting the selected one path of data to the third trigger, and the third trigger is used for outputting the data output by the data selector. The data transmission circuit reduces the path length and thus reduces the path delay.

Inventors

• YANG TAO
• QIN LEI

Assignees

• 海光信息技术(苏州)有限公司

Dates

Publication Date

20260512

Application Date

20260104

Claims (14)

1. 1. A data transmission circuit, comprising: The first-stage trigger is used for outputting data to the second-stage trigger module under the control of a clock signal output by the clock source; The second-stage trigger module comprises N+1 second triggers, wherein the input ends of the N+1 second triggers are connected with the output ends of the first-stage triggers, the updating period of output data of each second trigger is N+1 clock periods of the clock source, and the clock periods of each second trigger triggered are different, and N+1 is a natural number which is larger than or equal to 1; The third trigger module comprises a data selector and a third trigger which are connected, wherein the data selector is used for selecting one path from the multipath data output by the second trigger module in each clock period of the clock source and outputting the selected one path of data to the third trigger, and the third trigger is used for outputting the data output by the data selector under the control of the clock signal output by the clock source.
2. 2. The circuit of claim 1, wherein the second stage flip-flop module further comprises: and the N+1 trigger control units are connected with one second trigger, and are used for outputting a control signal every N+1 clock cycles of the clock source, and the control signal is used for controlling the corresponding second trigger to output the data input by the first-stage trigger.
3. 3. The circuit of claim 2, wherein the trigger control unit is a data selector or clock gating.
4. 4. The circuit of claim 2, wherein the circuit further comprises: And the control module is used for generating enabling signals of the N+1 trigger control units under the control of clock signals output by the clock source, wherein the enabling signals are N+1-bit single-hot codes.
5. 5. The circuit of claim 4, wherein the control module comprises: A cyclic accumulator for counting cycles of the clock signal of the clock source; And the input end of the enabling signal generating unit is connected with the output end of the circulating accumulator and is used for generating the enabling signal based on the accumulation result of the circulating accumulator.
6. 6. The circuit of claim 4, wherein the control module is further configured to generate a selection signal of the data selector, the selection signal being configured to control the data selector to select one of the plurality of paths of data output from the second stage flip-flop module, and output the selected one of the paths of data to the third flip-flop.
7. 7. The circuit of claim 6, wherein the control module comprises: A cyclic accumulator for counting cycles of the clock signal of the clock source; and the selection signal generation unit is used for beating the accumulation result of the cyclic accumulator to obtain the selection signal.
8. 8. A chip comprising the data transmission circuit of any one of claims 1-7.
9. 9. A method of data transmission, the method comprising: outputting data to a second-stage trigger module under the control of a clock signal output by a clock source through a first-stage trigger; triggering a second trigger in a second-stage trigger module to output data in the clock period of each clock source, wherein the update period of the output data of each second trigger is N+1 clock periods of the clock source, and the triggered clock periods of each second trigger are different; and selecting one path from the multipath data output by the second-stage trigger module by a data selector in the third-stage trigger module in each clock cycle of the clock source, and outputting the selected one path of data to a third trigger in the third-stage trigger module, so that the third trigger outputs the data output by the data selector under the control of a clock signal output by the clock source.
10. 10. The method of claim 9, wherein before triggering a second flip-flop in the second stage flip-flop module to output data in each clock cycle of the clock source, further comprising: Under the control of the clock signals output by the clock sources, outputting a control signal every N+1 clock cycles of the clock sources through each trigger control unit, wherein each trigger control unit comprises N+1 trigger control units, and each trigger control unit is used for controlling one second trigger; Triggering a second flip-flop in the second stage flip-flop module to output data in each clock cycle of the clock source, including: And triggering a second trigger in the second-stage trigger module to output data in each clock period of the clock source based on the control signal.
11. 11. The method according to claim 9, wherein the method further comprises: under the control of a clock signal output by a clock source, enabling signals of N+1 trigger control units are generated, and the enabling signals are N+1-bit single-hot codes.
12. 12. The method according to claim 9, wherein the method further comprises: and controlling the data selector to select one path from the multi-path data output by the second-stage trigger module according to the selection signal, and outputting the selected one path of data to the third trigger.
13. 13. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the method of any of claims 9 to 12.
14. 14. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor, implements the steps of the method of any of claims 9 to 12.

Description

Data transmission circuit, chip, data transmission method, medium, and program product Technical Field The present application relates to the field of chip technologies, and in particular, to a data transmission circuit, a chip, a data transmission method, a medium, and a program product. Background In the field of processors, particularly high performance CPU/DCU chips, a large amount of data transfer is required. For example, data transfer of a data bus to each high-speed IO interface (such as Serdes, PCIE, USB, etc.). These data transmissions are characterized by long wire distances, high frequencies, and large data bandwidths. Thus, such data transmission is typically implemented using a multi-level repeater (repeater). The forwarder is a pipeline (pipeline) consisting of full positive edge flip-flops (flip-flops). As the demand for data transmission bandwidth increases, the bus frequency increases continuously, and the timing of the flip-flops becomes difficult to converge. In the conventional technology, the number of flip-flop stages is increased on a data path, so that path delay between flip-flops of each stage is reduced, and the time sequence requirement of a target clock frequency is met. However, increasing the number of flip-flop stages results in an increase in path delay. Disclosure of Invention Based on this, it is necessary to provide a data transmission circuit, a chip, a data transmission method, a medium, and a program product capable of reducing the number of flip-flop stages and reducing path delay. In a first aspect, the present application provides a data transmission circuit comprising: The first-stage trigger is used for outputting data to the second-stage trigger module under the control of a clock signal output by the clock source; The second-stage trigger module comprises N+1 second triggers, wherein the input ends of the N+1 second triggers are connected with the output ends of the first-stage triggers, the updating period of output data of each second trigger is N+1 clock periods of the clock source, and the clock periods of each second trigger triggered are different, and N+1 is a natural number which is larger than or equal to 1; The third trigger module comprises a data selector and a third trigger which are connected, wherein the data selector is used for selecting one path from the multipath data output by the second trigger module in each clock period of the clock source and outputting the selected one path of data to the third trigger, and the third trigger is used for outputting the data output by the data selector under the control of the clock signal output by the clock source. In one embodiment, the second stage flip-flop module further comprises: and the N+1 trigger control units are connected with one second trigger, and are used for outputting a control signal every N+1 clock cycles of the clock source, and the control signal is used for controlling the corresponding second trigger to output the data input by the first-stage trigger. In one embodiment, the trigger control unit is a data selector or clock gating. In one embodiment, the circuit further comprises: And the control module is used for generating enabling signals of the N+1 trigger control units under the control of clock signals output by the clock source, wherein the enabling signals are N+1-bit single-hot codes. In one embodiment, the control module includes: A cyclic accumulator for counting cycles of the clock signal of the clock source; And the input end of the enabling signal generating unit is connected with the output end of the circulating accumulator and is used for generating the enabling signal based on the accumulation result of the circulating accumulator. In one embodiment, the control module is further configured to generate a selection signal of the data selector, where the selection signal is used to control the data selector to select one path from the multiple paths of data output by the second stage flip-flop module, and output the selected one path of data to the third flip-flop. In one embodiment, the control module includes: A cyclic accumulator for counting cycles of the clock signal of the clock source; and the selection signal generation unit is used for beating the accumulation result of the cyclic accumulator to obtain the selection signal. In a second aspect, the present application further provides a chip, including the data transmission circuit described above. In a third aspect, the present application further provides a data transmission method, the method including: outputting data to a second-stage trigger module under the control of a clock signal output by a clock source through a first-stage trigger; triggering a second trigger in a second-stage trigger module to output data in the clock period of each clock source, wherein the update period of the output data of each second trigger is N+1 clock periods of the clock source, and the triggered clock periods of each