CN-122021506-A - SRAM efficient automatic simulation method, equipment and medium based on graph learning and waveform propagation

Abstract

The invention discloses a high-efficiency automatic simulation method, equipment and medium of SRAM (static random Access memory) based on graph learning and waveform propagation, and relates to the field of electric digital data processing, the simulation method comprises the following steps of S1, carrying out heterogeneous graph modeling on an SRAM circuit to be simulated, and uniformly characterizing a standard unit and an interconnection line thereof as a graph structure with node characteristics and edge characteristics; S2, obtaining logic conversion information of each unit in the SRAM circuit, and constructing a global feature vector by combining fan-out information of the units, S3, inputting an input waveform, a graph structure and the global feature vector into a pre-constructed graph learning model, and predicting to obtain an output waveform of a single unit, S4, taking the output waveform predicted by a current stage unit as an input waveform of a next stage unit, and sequentially and iteratively executing S3 along a signal path until a final output waveform of the whole path is predicted. The invention greatly improves the simulation speed while maintaining high waveform prediction precision, and has good generalization capability for SRAM arrays of different scales.

Inventors

• YANG FAN
• Lu Beisi

Assignees

• 复旦大学

Dates

Publication Date

20260512

Application Date

20260413

Claims (10)

1. 1. The SRAM high-efficiency automatic simulation method based on graph learning and waveform propagation is characterized by comprising the following steps of: s1, carrying out heterogeneous graph modeling on an SRAM circuit to be simulated, and uniformly characterizing standard units and interconnection lines thereof in the SRAM circuit as graph structures with node characteristics and edge characteristics; S2, executing switch-level simulation, obtaining logic conversion information of each unit in the SRAM circuit, and constructing a global feature vector by combining fan-out information of the units; S3, inputting the input waveform, the graph structure and the global feature vector into a pre-constructed graph learning model, and predicting to obtain an output waveform of a single unit; S4, adopting a waveform propagation strategy, taking the output waveform predicted by the current stage unit as the input waveform of the next stage unit, and sequentially and iteratively executing the step S3 along the signal path until the final output waveform of the whole path is predicted.
2. 2. The method for efficient automatic simulation of SRAM based on graph learning and waveform propagation of claim 1, wherein the step of S1 comprises the following sub-steps: S11, respectively creating a transistor and a power grid as nodes of different types for a standard unit, wherein the characteristics of the transistor node comprise physical properties of the transistor node, and the characteristics of the power grid node comprise types and degrees of the power grid node; S12, estimating RC parasitic effect of the interconnection line by adopting a lumped pi model, and respectively creating the estimated resistance and capacitance as graph nodes, wherein the values of the graph nodes are used as the characteristics of the corresponding nodes; And S13, connecting the nodes of the standard unit and the interconnection line through edges according to the physical connectivity, and coding the connection types, so that the standard unit and the interconnection line are fused into a unified graph structure.
3. 3. The method of claim 1, wherein in the step S2, the logic conversion information at least comprises logic output values of units before and after a read-write operation, and the switch-level simulation is calculated based on only operation inputs of the SRAM circuit and logic functions of the units.
4. 4. The method for efficient and automatic simulation of SRAM based on graph learning and waveform propagation of claim 1, wherein in the step S3, the graph learning model comprises: The waveform characteristic extractor is used for extracting dynamic characteristics of the input waveform through a convolutional neural network and generating a waveform embedding vector; A topological feature extractor for inputting the nodes and edge features of the graph structure into a graph neural network with an attention mechanism to generate a topological embedded vector; The global feature extractor is used for carrying out linear transformation on the global feature vector to generate a global embedded vector; and the prediction module is used for splicing the waveform embedding vector, the topology embedding vector and the global embedding vector and outputting a predicted waveform through the multi-layer perceptron.
5. 5. The method of SRAM efficient automatic simulation based on graph learning and waveform propagation of claim 4 wherein graph neural network in said topology feature extractor takes edge features in said graph structure as part of input to dynamically learn importance of neighboring nodes when computing attention scores.
6. 6. The method of claim 1, wherein in the step S4, the waveform propagation strategy includes discretizing the input waveform and the output waveform to represent a complete waveform using a predetermined number of time points corresponding to the moments when the voltage rises or falls to the power supply voltage VDD at the scale of 0.05, 0.10, 0.15, 0.90, 0.95.
7. 7. The method of claim 1, wherein in the step S4, the waveform prediction processes of the plurality of signal paths in the SRAM circuit are processed in parallel.
8. 8. The method of claim 1, wherein the historic memory dependency of the sequential elements in the SRAM circuit is characterized by using the logic conversion information calculated in the switch level simulation as a part of the global feature vector.
9. 9. An electronic device comprising at least one processor, and a memory communicatively coupled to at least one of the processors; Wherein the memory stores a computer program for execution by at least one of the processors, the computer program being executable by at least one of the processors to enable the at least one of the processors to perform the graph learning and waveform propagation based SRAM efficient auto-simulation method of any one of claims 1-7.
10. 10. A computer readable storage medium storing computer instructions for causing a processor to implement the graph learning and waveform propagation based SRAM efficient automatic simulation method of any one of claims 1-7 when executed.

Description

SRAM efficient automatic simulation method, equipment and medium based on graph learning and waveform propagation Technical Field The invention relates to the technical field of electric digital data processing, in particular to an integrated circuit computer aided design, and specifically relates to an SRAM efficient automatic simulation method, equipment and medium based on graph learning and waveform propagation. Background Static Random Access Memory (SRAM) is a core component of data-intensive system-on-chip, and occupies a significant portion of the chip area in modern digital integrated circuits. With the continuous evolution of integrated circuit process nodes, the SRAM design scale under advanced processes is increasingly large, and accurate timing characterization is critical to ensure functional correctness and reliability of the overall chip. The timing performance of a high-speed SRAM array not only determines the highest operating frequency of the chip, but also directly affects the power consumption and stability of the system. However, with process scaling, the parasitic effects of resistance and capacitance caused by the interconnect lines are more remarkable, especially on long word lines and bit lines, and the problem of signal timing degradation is serious, further increasing the complexity of timing analysis. At present, transistor-level SPICE simulation is mainly adopted in the industry and academia to carry out timing characterization of SRAM. The method obtains a high-precision voltage waveform by solving a nonlinear differential equation, but the calculation complexity of the method increases in proportion to the number n of bit cells in the SRAM array by O (n 3). For large-scale custom designs, complete SPICE simulations often take months or even cannot be completed. To alleviate this bottleneck, conventional acceleration methods include critical path extraction, fast-SPICE simulation, and RC reduction techniques, which reduce the amount of computation by simplifying the circuit model or reducing the simulation nodes, but inevitably produce a non-negligible loss in waveform accuracy. In recent years, emerging machine learning methods such as bayesian optimization, transformer and conventional Graph Neural Network (GNN) are gradually introduced into the field of SRAM design, but the existing work is focused on yield optimization or simple time delay numerical prediction, and cannot output complete waveforms containing abundant information such as slopes and signal integrity, so that the actual requirements of industry on accurate path waveform simulation are difficult to meet. Disclosure of Invention The invention overcomes the defects of the prior art, provides a SRAM high-efficiency automatic simulation method, equipment and medium based on graph learning and waveform propagation, fuses SRAM standard cell topology and interconnection line RC parasitic effect into a unified graph structure through heterographic modeling, then utilizes a high-speed switch level simulation to extract logic state and fan-out information to support memory modeling of a time sequence element, finally completes high-precision waveform prediction by means of a multi-branch model fusing a convolution network and an attention seeking neural network, and realizes full-path time sequence analysis by combining a discretization waveform propagation strategy, thereby realizing spanning type improvement of simulation efficiency while maintaining SPICE level precision. In order to achieve the purpose, the technical scheme adopted by the invention is that in the first aspect, the invention provides an SRAM high-efficiency automatic simulation method based on graph learning and waveform propagation, which comprises the following steps: s1, carrying out heterogeneous graph modeling on an SRAM circuit to be simulated, and uniformly characterizing standard units and interconnection lines thereof in the SRAM circuit as graph structures with node characteristics and edge characteristics; S2, executing switch-level simulation, obtaining logic conversion information of each unit in the SRAM circuit, and constructing a global feature vector by combining fan-out information of the units; S3, inputting the input waveform, the graph structure and the global feature vector into a pre-constructed graph learning model, and predicting to obtain an output waveform of a single unit; S4, adopting a waveform propagation strategy, taking the output waveform predicted by the current stage unit as the input waveform of the next stage unit, and sequentially and iteratively executing the step S3 along the signal path until the final output waveform of the whole path is predicted. In a preferred embodiment of the present invention, in the step S1, the method includes the following substeps: S11, respectively creating a transistor and a power grid as nodes of different types for a standard unit, wherein the characteristics of the transistor