CN-122021507-A - FPGA online differential test method, device, equipment and storage medium

Abstract

The embodiment of the specification relates to the technical field of simulation test and provides an FPGA online differential test method, device, equipment and storage medium, wherein the method comprises the steps of controlling an FPGA platform to be tested to execute a target program; after executing one instruction, if the current instruction is of a first target instruction type, acquiring register state information of the FPGA platform to be tested when executing the current instruction as first comparison state information, acquiring register state information of a reference platform when executing the current instruction as first reference state information according to offline tracking data, comparing the first comparison state information with the first reference state information, and outputting a differential test result of the FPGA platform to be tested according to a comparison result. According to the embodiment of the specification, the FPGA can be subjected to online differential test so as to quickly locate errors.

Inventors

• TENG XIANGMING

Assignees

• 成都群芯微电子科技有限公司

Dates

Publication Date

20260512

Application Date

20260115

Claims (20)

1. 1. An on-line differential testing method for an FPGA, which is characterized by being applied to a debugger side and comprising the following steps: controlling the FPGA platform to be tested to execute the target program; after executing one instruction, if the current instruction is of a first target instruction type, acquiring register state information of the FPGA platform to be tested when executing the current instruction as first state information to be compared; acquiring register state information when a reference platform executes a current instruction according to offline tracking data as first reference state information; Comparing the first state information to be compared with the first reference state information; And outputting a differential test result of the FPGA platform to be tested according to the comparison result.
2. 2. The method of claim 1, wherein the first target instruction type is a user-level instruction, and wherein the determining of the first target instruction type includes: And if the PC value of the current instruction is smaller than a preset threshold value, judging the current instruction as the first target instruction type.
3. 3. The method of claim 1, wherein the first to-be-compared state information includes at least a PC value of the current instruction and all current general purpose register values.
4. 4. The method of claim 1, wherein the offline tracking data is register state data stored offline during execution of the target program by the reference platform, and the offline tracking data includes a PC value recorded in an instruction execution order and destination register value change information corresponding to each instruction after execution.
5. 5. The method of claim 4, wherein the fetching register state information of the reference platform when executing the current instruction as the first reference state information comprises: Acquiring a PC value of the current instruction from the offline tracking data; reconstructing according to the offline tracking data according to the instruction execution sequence to obtain all the general register values corresponding to the current instruction executed by the reference platform; and taking the PC value of the current instruction and all general register values as the first reference state information.
6. 6. The method of claim 5, wherein reconstructing in instruction execution order from the offline trace data to obtain all general purpose register values corresponding to the current instruction executed by the reference platform comprises: sequentially reading the PC value of each instruction in the offline tracking data and the corresponding destination register value change information; updating the corresponding general register value in the register state dictionary according to the change information of the corresponding target register value of each instruction; comparing the PC value of the read instruction with the PC value of the current instruction; if the comparison results are consistent, taking all the updated general register values in the register state dictionary as all the general register values corresponding to the current instruction executed by the reference platform; If the comparison result is inconsistent, the next instruction is continuously read, and the step of updating the corresponding general register value in the register state dictionary according to the change information of the target register value corresponding to each instruction is executed until the comparison result is consistent.
7. 7. A method according to claim 3, wherein comparing the first state information to be compared with the first reference state information comprises: if the PC value and all the register values in the first state information to be compared are identical to the PC value and all the register values in the first reference state information, judging that the current instruction test passes, and continuously executing the next instruction; if the comparison is inconsistent, terminating the execution of the target program of the FPGA platform to be tested, and outputting corresponding error information.
8. 8. The FPGA online differential testing method is characterized by being applied to a reference platform side and comprising the following steps of: Acquiring and analyzing offline tracking data generated when a target program is executed by a reference platform to obtain an instruction execution sequence and corresponding register state information; identifying a target instruction belonging to a second target instruction type from the instruction execution sequence to form an instruction sequence to be compared; Determining second reference state information corresponding to each target instruction in the instruction sequence to be compared according to the register state information; Controlling the FPGA platform to be tested to pause at each target instruction in the instruction sequence to be compared; acquiring register state information of the FPGA platform to be tested when a target instruction is executed as second state information to be compared; Comparing the second state information to be compared with the second reference state information; And outputting a differential test result of the FPGA platform to be tested according to the comparison result.
9. 9. The method of claim 8, wherein the second target instruction type is a user-level branch instruction, and wherein identifying a target instruction from the instruction execution sequence that belongs to the second target instruction type comprises: if the PC value of the instruction is smaller than the preset threshold value and the instruction is a branch instruction, the instruction is judged to be a target instruction belonging to the second target instruction type.
10. 10. The method of claim 8, wherein controlling the FPGA platform under test to pause at execution to each target instruction in the sequence of instructions to be aligned, comprises: a command is sent to the debugger to set a breakpoint at the target instruction.
11. 11. The method of claim 10, wherein the breakpoint is automatically deleted after a trigger.
12. 12. The method of claim 8, wherein the second to-be-aligned state information includes a PC value of a current target instruction and current all general purpose register values.
13. 13. The method of claim 8, wherein the offline tracking data is register state data stored offline during execution of the target program by the reference platform, and the offline tracking data includes a PC value recorded in an instruction execution sequence and corresponding destination register value change information after execution of each instruction.
14. 14. The method of claim 13, wherein determining second reference state information corresponding to each target instruction in the sequence of instructions to be aligned according to the register state information comprises: sequentially reading the PC value of each target instruction in the instruction sequence to be compared and the corresponding target register value change information; updating the corresponding general register value in the register state dictionary according to the change information of the target register value corresponding to each target instruction; Comparing the PC value of the read target instruction with the PC value of the target instruction to be compared currently; if the comparison results are consistent, taking the PC value of the current target instruction to be compared and all the updated general register values in the register state dictionary as second reference state information of the current target instruction to be compared; If the comparison result is inconsistent, the next instruction is continuously read, and the step of updating the corresponding general register value in the register state dictionary according to the change information of the target register value corresponding to each target instruction is executed until the comparison result is consistent.
15. 15. The method of claim 14, wherein comparing the second to-be-compared state information with the second reference state information comprises: If the PC value and all the register values in the second to-be-compared state information are identical to the PC value and all the register values in the second reference state information, judging that the corresponding target instruction passes the test, and continuously executing the next instruction; if the comparison is inconsistent, terminating the execution of the target program of the FPGA platform to be tested, and outputting corresponding error information.
16. 16. An on-line differential testing device for an FPGA, which is applied to a debugger side, and includes: The first control module is used for controlling the FPGA platform to be tested to execute the target program; the first acquisition module is used for acquiring register state information of the FPGA platform to be tested when executing the current instruction as first to-be-compared state information if the current instruction is of a first target instruction type after executing one instruction; The second acquisition module is used for acquiring register state information when the reference platform executes the current instruction according to the offline tracking data as first reference state information; The first comparison module is used for comparing the first state information to be compared with the first reference state information; And the first output module is used for outputting the differential test result of the FPGA platform to be tested according to the comparison result.
17. 17. An on-line differential testing device for an FPGA, wherein the device is applied to a reference platform side, and includes: the third acquisition module is used for acquiring and analyzing the offline tracking data generated when the reference platform executes the target program to obtain an instruction execution sequence and corresponding register state information; The identification module is used for identifying a target instruction belonging to a second target instruction type from the instruction execution sequence to form an instruction sequence to be compared; the determining module is used for determining second reference state information corresponding to each target instruction in the instruction sequence to be compared according to the register state information; The second control module is used for controlling the FPGA platform to be tested to pause at each target instruction in the instruction sequence to be compared; The fourth acquisition module is used for acquiring register state information of the FPGA platform to be tested when the target instruction is executed as second state information to be compared; the second comparison module is used for comparing the second state information to be compared with the second reference state information; and the second output module is used for outputting the differential test result of the FPGA platform to be tested according to the comparison result.
18. 18. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements the method of any one of claims 1 to 15 when the computer program is executed.
19. 19. A computer readable storage medium, characterized in that the computer readable storage medium stores a computer program which, when executed by a processor, implements the method according to any one of claims 1 to 15.
20. 20. A computer program product comprising at least one instruction or at least one program, the at least one instruction or the at least one program being loaded and executed by a processor to implement the method of any one of claims 1 to 15.

Description

FPGA online differential test method, device, equipment and storage medium Technical Field The embodiment of the specification relates to the technical field of simulation test, in particular to an FPGA online differential test method, device, equipment and storage medium. Background With the continuous increase of the design complexity of integrated circuits, the verification link in the chip design process becomes more and more critical. After the register transfer level design is completed, the design typically requires multiple levels of verification, including software simulation, hardware simulation, and prototype verification on field programmable gate arrays. The design is programmed to the FPGA platform for verification, and therefore, the FPGA platform can operate at a clock speed close to that of a real chip, and provides a real hardware timing environment, which is an indispensable tool in the design flow of the processor. To ensure the correctness of the design function, differential testing is an effective means for widespread use. The test principle is that the same test stimulus is respectively applied to two design implementations conforming to the same specification, and whether the output or internal states of the two design implementations are consistent is compared to find potential errors. The existing differential test method only supports differential tests among simulators, simulation platforms or between simulators and simulation platforms. In the actual chip development process, after verification by the simulator and the simulation platform, the chip design is also required to be programmed into the FPGA to perform a verification process with higher accuracy. When the design is integrated and deployed to the FPGA platform, the prior art does not support a direct comparison of the actual hardware behavior that will run on the FPGA with the fully validated simulator or simulation platform behavior. The developer usually can only rely on simple comparison or long-time system level test based on output results, once errors are found, the positioning process is extremely difficult, and a great deal of time is required for waveform debugging or log analysis, so that the efficiency is low. Therefore, there is a need for an on-line differential testing method for an FPGA to make up for the blank that the FPGA platform cannot utilize differential testing to quickly locate errors. Disclosure of Invention Aiming at the problems in the prior art, an object of an embodiment of the present disclosure is to provide an on-line differential testing method, an on-line differential testing device, and a storage medium for an FPGA, so as to solve the problem that an FPGA platform cannot utilize differential testing to perform quick positioning errors in the prior art. In order to solve the above technical problems, the specific technical solutions of the embodiments of the present specification are as follows: In one aspect, an embodiment of the present disclosure provides an FPGA online differential testing method, where the method is applied to a debugger side, including: controlling the FPGA platform to be tested to execute the target program; after executing one instruction, if the current instruction is of a first target instruction type, acquiring register state information of the FPGA platform to be tested when executing the current instruction as first state information to be compared; acquiring register state information when a reference platform executes a current instruction according to offline tracking data as first reference state information; Comparing the first state information to be compared with the first reference state information; And outputting a differential test result of the FPGA platform to be tested according to the comparison result. Further, the first target instruction type is a user-level instruction, and the determining manner of the first target instruction type includes: And if the PC value of the current instruction is smaller than a preset threshold value, judging the current instruction as the first target instruction type. Further, the first to-be-compared state information at least comprises a PC value of the current instruction and all current general register values. Further, the offline tracking data is register state data stored offline in the process of executing the target program by the reference platform, and comprises PC values recorded according to the instruction execution sequence and corresponding target register value change information after each instruction is executed. Further, the obtaining the register state information of the reference platform when executing the current instruction as the first reference state information includes: Acquiring a PC value of the current instruction from the offline tracking data; reconstructing according to the offline tracking data according to the instruction execution sequence to obtain all the general reg