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CN-122021509-A - Booth mixed coding multiplier design method and device

CN122021509ACN 122021509 ACN122021509 ACN 122021509ACN-122021509-A

Abstract

The application relates to the technical field of computers and provides a method and a device for designing a multiplier of a booth hybrid code, wherein the method comprises the steps of determining an expression of a multiplier, wherein the expression is represented by a plurality of booth3 code items and booth2 code items, determining an operand of the booth3 code partial product according to the expression of a multiplicand and a multiplier and a booth3 code partial product selection logic, transforming the operand of the booth3 code partial product by using a constant K to obtain a redundant partial product, carrying out alignment processing on the booth2 code partial product and the redundant partial product, designing a multiplier circuit according to the aligned partial product and a partial product of a compensation coefficient, and determining the compensation coefficient according to the booth3 code partial product and the constant K. The application can reduce the number of partial products on the basis of not introducing a large bit width adder, thereby reducing the number of compressors and finally reducing the consumption and time delay of hardware resources.

Inventors

  • SHENG QILONG

Assignees

  • 成都群芯微电子科技有限公司

Dates

Publication Date
20260512
Application Date
20260115

Claims (12)

  1. 1. A method for designing a multiplier of a booth hybrid code is characterized by comprising the following steps: determining an expression of a multiplier, the expression represented by a plurality of booth3 encoding terms and booth2 encoding terms; Determining a booth3 encoding partial product and a booth2 encoding partial product according to the multiplicand, the expression of the multiplier, the booth3 encoding partial product selection logic and the booth2 encoding partial product selection logic; Transforming the booth3 coding partial product by using a constant K to obtain a redundant partial product, wherein the bits of a plurality of preset bits in the constant K are 1, and the rest bits are 0; carrying out alignment processing on the booth2 coding partial product and the redundant partial product; And designing a multiplier circuit according to the aligned partial products and the partial products of the compensation coefficients, wherein the compensation coefficients are determined according to the quantity of the Booth3 coding partial products and a constant K.
  2. 2. The method of claim 1 wherein bits 0 through 31 and bits 61 through 63 in the multiplier are represented by a booth2 encoded partial product and bits 31 through 61 in the multiplier are represented by a booth3 encoded partial product when the multiplier is 64 bits.
  3. 3. The method of claim 1, wherein transforming the booth3 encoded partial product with a constant K results in a redundant partial product, comprising: if the booth3 encoded partial product is 3X, X is the multiplicand, then the redundant partial product of 3X is determined using the following operations: Moving the multiplicand X to the left by 1 bit to obtain data 2X; aligning the data 2X with the multiplicand X; Starting from bit 1, grouping the multiplicand X and bits in data 2X according to the preset bits; Adding the multiplicand X and the data of the same group in the data 2X to obtain a carry bit C and data 3X; And adding the constant K and the data 3X to obtain a redundant partial product K+3X of 3X, wherein a preset bit in the constant K is the position of a carry bit C.
  4. 4. The method of claim 3, wherein transforming the booth3 encoded partial product with a constant K results in a redundant partial product, further comprising: If the booth3 encoded partial product is-3X, the redundant partial product of-3X is determined using the following operations: And inverting the non-blank part of the redundant partial product K+3X of 3X and then adding 1 to obtain the redundant partial product K-3X of-3X.
  5. 5. The method of claim 1, wherein transforming the booth3 encoded partial product with a constant K results in a redundant partial product, comprising: if the booth3 encoded partial product is X and-X, X is a multiplicand, determining the redundant partial product of X and the redundant partial product of-X by: adding the constant K and the multiplicand X to obtain a redundant partial product K+X of X; And carrying out inversion and then adding 1 on the non-blank part of the redundant partial product K+X of the X to obtain the redundant partial product K-X of the-X.
  6. 6. The method of claim 1, wherein transforming the booth3 encoded partial product with a constant K results in a redundant partial product, comprising: If the booth3 encoded partial product is 2X and-2X, X is the multiplicand, then the redundant partial product of 2X and the redundant partial product of-2X are determined by: Moving the multiplicand X to the left by 1 bit to obtain data 2X; Adding the constant K and the data 2X to obtain a redundant partial product K+2X of 2X; And inverting the non-blank part of the redundancy part product K+2X of 2X and then adding 1 to obtain a redundancy part product K-2X of-2X.
  7. 7. The method of claim 1, wherein transforming the booth3 encoded partial product with a constant K results in a redundant partial product, comprising: if the booth3 encoded partial product is 4X and-4X, X is the multiplicand, then the redundant partial product of 4X and the redundant partial product of-4X are determined using the following operations: Moving the multiplicand X to the left by 2 bits to obtain data 4X; adding the constant K and the data 4X to obtain a redundant partial product K+4X of 4X; and inverting the non-blank part of the redundant partial product K+4X of 4X and then adding 1 to obtain the redundant partial product K-4X of-4X.
  8. 8. The method of claim 1, wherein designing the multiplier circuit based on the aligned partial products and the partial products of the compensation coefficients comprises: Compressing the partial product of the aligned partial product and the compensation coefficient by adopting a 4-2 compressor and a 3-2 compressor; And adding partial products obtained by the 4-2 compressor and the 3-2 compressor by using a full adder to obtain a multiplication result.
  9. 9. A booth hybrid coded multiplier design apparatus, comprising: a representation unit for determining an expression of the multiplier, the expression being represented by a plurality of booth3 encoded items and booth2 encoded items; a selection unit for determining a booth3 encoding partial product and a booth2 encoding partial product according to the multiplicand, the expression of the multiplier, the booth3 encoding partial product selection logic, and the booth2 encoding partial product selection logic; The transformation unit is used for transforming the booth3 coding partial product by using a constant K to obtain a redundant partial product, wherein the bits of a plurality of preset bits in the constant K are 1, and the rest bits are 0; an alignment unit, configured to perform alignment processing on the booth2 encoding partial product and the redundancy partial product; And the design unit is used for designing a multiplier circuit according to the aligned partial products and the partial products of the compensation coefficients, wherein the compensation coefficients are determined according to the quantity of the booth3 coding partial products and a constant K.
  10. 10. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the method of any one of claims 1 to 8 when executing the computer program.
  11. 11. A computer readable storage medium storing a computer program, characterized in that the computer program, when executed by a processor of a computer device, implements the method of any one of claims 1 to 8.
  12. 12. A computer program product comprising a computer program, characterized in that the computer program, when executed by a processor of a computer device, implements the method of any one of claims 1 to 8.

Description

Booth mixed coding multiplier design method and device Technical Field The application relates to the technical field of computers, and particularly provides a method and a device for designing a boot hybrid coded multiplier. Background In the prior art, the Booth method-based multiplier comprises a Booth2 code-based multiplier and a Booth3 code-based multiplier. The multiplier based on booth2 code has more partial products, so more hardware resources are needed, and calculation delay is increased for multiplication with larger bit width. Compared with the multiplier based on the booth2 code, the multiplier based on the booth3 code needs to obtain 3X additionally, and has the problem of complex logic. The 3X partial product requires an additional 64-bit adder, which increases hardware resources and also increases computation delay. Disclosure of Invention The application provides a method and a device for designing a boot hybrid code multiplier, which are used for solving the problems of hardware resource requirement and calculation delay of the existing multiplier. In order to solve the above technical problems, an aspect of the present application provides a method for designing a multiplier with booth hybrid encoding, including: determining an expression of a multiplier, the expression represented by a plurality of booth3 encoding terms and booth2 encoding terms; Determining a booth3 encoding partial product and a booth2 encoding partial product according to the expression of a multiplicand and a multiplier, a booth3 encoding partial product selection logic and a booth2 encoding partial product selection logic, and transforming the booth3 encoding partial product by using a constant K to obtain a redundant partial product, wherein a plurality of preset bits in the constant K are 1, and the rest bits are 0; carrying out alignment processing on the booth2 coding partial product and the redundant partial product; And designing a multiplier circuit according to the aligned partial products and the partial products of the compensation coefficients, wherein the compensation coefficients are determined according to the quantity of the Booth3 coding partial products and a constant K. In a further embodiment of the present application, when the multiplier is 64 bits, bits 0 to 31 and bits 61 to 63 in the multiplier are represented by a booth2 encoded partial product, and bits 31 to 61 in the multiplier are represented by a booth3 encoded partial product. In a further embodiment of the present application, transforming the booth3 encoded partial product with a constant K to obtain a redundant partial product includes: if the booth3 encoded partial product is 3X, X is the multiplicand, then the redundant partial product of 3X is determined using the following operations: Moving the multiplicand X to the left by 1 bit to obtain data 2X; aligning the data 2X with the multiplicand X; Starting from bit 1, grouping the multiplicand X and bits in data 2X according to the preset bits; Adding the multiplicand X and the data of the same group in the data 2X to obtain a carry bit C and data 3X; And adding the constant K and the data 3X to obtain a redundant partial product K+3X of 3X, wherein a preset bit in the constant K is the position of a carry bit C. In a further embodiment of the present application, transforming the booth3 encoded partial product with a constant K to obtain a redundant partial product, further includes: If the booth3 encoded partial product is-3X, the redundant partial product of-3X is determined using the following operations: And inverting the non-blank part of the redundant partial product K+3X of 3X and then adding 1 to obtain the redundant partial product K-3X of-3X. In a further embodiment of the present application, transforming the booth3 encoded partial product with a constant K to obtain a redundant partial product includes: if the booth3 encoded partial product is X and-X, X is a multiplicand, determining the redundant partial product of X and the redundant partial product of-X by: adding the constant K and the multiplicand X to obtain a redundant partial product K+X of X; And carrying out inversion and then adding 1 on the non-blank part of the redundant partial product K+X of the X to obtain the redundant partial product K-X of the-X. In a further embodiment of the present application, transforming the booth3 encoded partial product with a constant K to obtain a redundant partial product includes: if the number of the booth3 encoded partial product is 2X and-2X, X is the multiplicand, the redundant partial product of 2X and the redundant partial product of-2X are determined by the following operations: Moving the multiplicand X to the left by 1 bit to obtain data 2X; Adding the constant K and the data 2X to obtain a redundant partial product K+2X of 2X; And inverting the non-blank part of the redundancy part product K+2X of 2X and then adding 1 to obtain a redundancy part product K-2X of