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CN-122021510-A - FPGA simulation problem reproduction method based on wireshark packet grabbing and time sequence reconstruction

CN122021510ACN 122021510 ACN122021510 ACN 122021510ACN-122021510-A

Abstract

The invention relates to the field of FPGA simulation verification technology, and discloses an FPGA simulation problem reproduction method based on wireshark packet grabbing and time sequence reconstruction, which comprises the steps of deploying an wireshark tool at a network access node of a DUT in a network environment in which the FPGA actually operates, and capturing and storing network traffic received and transmitted by the DUT; the method comprises the steps of carrying out protocol analysis on captured messages, marking classified messages, screening a message set to be injected, generating a marked message queue, carrying out time sequence reconstruction, generating a transaction according to the reconstructed time sequence in a sequencer component of a UVM simulation platform, converting the transaction into an interface signal of a DUT, injecting the DUT according to a designated time sequence, comparing expected output of the DUT with an injected output response to obtain simulation result output, correlating the simulation result output with injection time and marking information of each message, and determining message characteristics causing problems. The method can truly simulate the actual test scene, and improve the reproduction rate and the positioning efficiency of the FPGA simulation problem.

Inventors

  • CHEN BO
  • YAN WEIMIN
  • CHEN KEYANG

Assignees

  • 南京全信传输科技股份有限公司

Dates

Publication Date
20260512
Application Date
20251216

Claims (10)

  1. 1. The FPGA simulation problem reproduction method based on wireshark packet grabbing and time sequence reconstruction is characterized by comprising the following steps of: Step 1, in a network environment in which an FPGA actually operates, deploying wireshark tools at a network access node of a DUT (device under test) to capture and store network traffic received and transmitted by the DUT; Step 2, carrying out protocol analysis on the message captured by the wireshark tool, identifying the protocol to which the message belongs according to the protocol configuration file, extracting key fields, classifying the message, identifying and marking the classified message; step 3, screening a message set to be injected according to a preset screening mode, and generating a marked message queue; Step 4, according to the injection mode selected by the user, carrying out time sequence reconstruction on the screened message queue; step 5, generating a transaction in sequencer modules of the UVM simulation platform according to the reconstructed time sequence, converting the transaction into an interface signal of the DUT, and injecting the interface signal into the DUT according to the appointed time sequence; And 6, comparing the expected output of the DUT with the injected output response to obtain simulation result output, correlating the simulation result output with the injection time and the marking information of each message, and determining the message characteristics causing the problem.
  2. 2. The FPGA simulation problem reproduction method based on wireshark packet grabbing and time sequence reconstruction according to claim 1, wherein in step 1, for a packet captured by a wireshark tool, a frame structure, a protocol header and load data of an original packet are reserved and stored as a standard pcap file format.
  3. 3. The method for simulating the problem reproduction of the FPGA based on wireshark packet capturing and time sequence reconstruction according to claim 1 is characterized in that in step 1, a library of libpcap is adopted to analyze the pcap file for the stored messages in a standard pcap file format, and core metadata of each message is extracted in batches to generate a structured data list.
  4. 4. The FPGA simulation problem reproduction method based on wireshark packet capturing and timing reconstruction according to claim 1, wherein in step 2, according to the protocol analysis of the packet captured by the wireshark tool, the protocol to which the packet belongs is identified according to the protocol configuration file, the key field is extracted, the packet is classified, and the classified packet is identified and marked, including: Carrying out multi-level protocol analysis according to the protocol configuration file, realizing protocol stack analysis of an Ethernet layer, a network layer, a transmission layer and an application layer, and extracting static characteristics and dynamic characteristics of a message, wherein the static characteristics comprise protocol identifiers, message length modes and address range fields of the message, and the dynamic characteristics comprise association relations among the messages and flow time sequence modes; Based on the preset rules and the classification model of the protocol feature library, the message matching classification is carried out, and the protocol type, the function role and the correlation are identified and marked.
  5. 5. The method for FPGA simulation problem reproduction based on wireshark packet capturing and time sequence reconstruction according to claim 4, wherein the performing packet matching classification, identifying and marking protocol types, function roles and correlations based on the preset rules and classification models of the protocol feature library includes: For each message, comparing the characteristic field of the message with a preset rule layer by layer, and marking the corresponding protocol type if the matching is successful; Based on message content and protocol specification, identifying the functional roles of the message in the communication process, including heartbeat packet, data request, data response, malformed message, attack message and connection establishment/disconnection; Based on the protocol matching degree, the function role correlation and the DUT interface binding matching degree, a correlation mark is obtained through weighted summation, and the correlation between the message and the DUT is quantized to distinguish the key flow, the common flow and the background flow.
  6. 6. The FPGA simulation problem reproduction method based on wireshark packet grabbing and timing reconstruction according to claim 5, wherein in step 3, the preset screening mode includes: A strict mode, namely reserving a message with protocol type matching and function role correlation and correlation marks more than or equal to 0.9; A loose mode, namely reserving a message with a protocol type belonging to a target protocol family and a correlation mark being more than or equal to 0.5; the abnormal priority mode is to reserve the abnormal message, attack message and abnormal response message, and supplement the key flow message; A combination mode, which is to support user-defined condition combination; And generating a marked message queue for the messages screened and combined by the user, wherein each message comprises original frame data, metadata, a correlation mark and an original timestamp.
  7. 7. The FPGA simulation problem reproduction method based on wireshark packet grabbing and timing reconstruction according to claim 1, wherein in step 4, the performing timing reconstruction on the screened message queue according to the injection mode selected by the user includes: Extracting a time stamp of a first message in the marked message queue as a reference time T0, and calculating a relative time offset delta tn=Tn-T0 of each message, wherein Tn is a message original time stamp; identifying a flow mode comprising periodic flow, burst flow and interactive flow by counting message time intervals; the relative time offset deltatn is adjusted based on different traffic patterns according to the injection pattern selected by the user, generating an injection timestamp t_object_n.
  8. 8. The FPGA simulation problem reproduction method based on wireshark packet grabbing and timing reconstruction of claim 7, wherein adjusting the relative time offset Δtn based on different traffic patterns according to the injection mode selected by the user generates an injection timestamp t_object_n, comprising: an accurate replay mode, wherein T_object_n=delta tn+random time jitter, the original relative time interval is reserved, and the range of the random time jitter is +/-5 ns; a normalization mode, t_object_n=Δtn×k, k is a time scaling factor, and a relative timing ratio is maintained; the event triggering mode is to adjust the injection time of the front and rear messages according to different flow modes by taking the triggering message as a reference; Pressure test mode t_object_n=n×Δt_fixed, Δt_fixed is a fixed small interval, the original time interval is ignored, and injection is at maximum rate.
  9. 9. The FPGA simulation problem reproduction method based on wireshark packet grabbing and timing reconstruction according to claim 1, wherein in step 5, in the sequencer component of the UVM simulation platform, a transaction is generated according to the reconstructed timing and converted into an interface signal of the DUT, and the DUT is injected according to the specified timing, including: ordering the marked message queues according to the adjusted injection time stamp T_object_n, generating a global injection time line, and determining the injection sequence and time point of each message; Detecting whether a plurality of messages need to be injected at the same time point, if so, adjusting delay injection time delay according to the priority of the data flow, wherein the priority of the data flow is set as that the key flow is greater than the common flow and greater than the background flow; Sequentially reading the marked message queue and the corresponding injection time stamp, initializing the current simulation time, entering a message sending cycle, calculating the waiting time, the waiting time sequence, packaging and sending a Transaction to a driver component frame by cycling through the message queue, and updating the current time current_time=t_object_n; And receiving the transaction sent by the sequencer module at the driver module, analyzing the original frame data, converting the frame data into corresponding interface signals according to the interface protocol of the DUT, driving the interface signals at the appointed beat of the simulation clock strictly according to the injection time stamp, and injecting the message into the DUT.
  10. 10. The method for reconstructing FPGA simulation problems based on wireshark packet grabbing and time sequence reconstruction according to claim 1, wherein comparing the expected output of the DUT with the injected output response to obtain simulation result output, correlating the simulation result output with the injection time and the marking information of each message, and determining the message characteristics causing the problems, comprises: constructing a behavior level reference model based on the protocol specification and the function requirement of the DUT, inputting the behavior level reference model into the injected message data, and outputting the behavior level reference model into the expected DUT response; receiving an output signal of the DUT and expected output of a reference model in real time, and performing comparison according to a message unique ID, wherein the comparison dimension comprises response time, output data content, state code, protocol format validity, and recording a comparison result (PASS/FAIL) and failure reasons of each message; And (3) injecting mark information and a comparison result according to the message unique ID association to form an association matrix, and carrying out feature aggregation on the message which causes failure to extract a commonality mark.

Description

FPGA simulation problem reproduction method based on wireshark packet grabbing and time sequence reconstruction Technical Field The invention relates to the technical field of FPGA simulation verification, and discloses an FPGA simulation problem reproduction method based on wireshark packet capturing and time sequence reconstruction. Background The excitation input by the FPGA-UVM simulation platform based on UVM construction is poured by a driver component of the in_agent, as shown in FIG. 1, the excitation is generated by a sequence component in a case, and the format is a transaction common to the UVM simulation platform. As shown in FIG. 1, the case module contains an excitation generator sequence responsible for generating various types of simulated excitation. The in agent component is an input agent. The device comprises a driver and a monitor, wherein the driver is used for converting the transaction into an interface signal which can be identified by the DUT, the monitor is used for collecting the excitation injected into the DUT and synchronously transmitting the excitation to ref_ bfm (reference model). The ref_ bfm module is used for simulating ideal behavior of the DUT and outputting expected results according to the stimulus input by the in_agent. The DUT module is an FPGA design to be tested (core verification object), receives the excitation of the in_agent, executes own logic and outputs a result. The out_agent module is an output agent, comprising a monitor, for collecting the actual output of the DUT and sorting it into a format recognizable by the score_board. The score_board module is used for core comparison, receiving the expected result of ref_ bfm and the actual result of out_agent, and comparing the expected result and the actual result to be consistent. The UVM-sequencer component is used as an arbiter for managing the communication between sequences and drivers, so that the excitation conflict when multiple sequences are concurrent is solved, the sequential and conflict-free transmission of the sequences to the drivers is ensured, and the excitation injection order is ensured. The transactions that can be constructed in the simulation environment are constructed according to the supported common protocols, but the stimulus that is poured onto the board in the actual FPGA board environment is sent by the opposite terminal device and is processed by some links or intermediate devices, so that some message types that are not considered by the logic development and verification staff exist in the message that arrives at the FPGA board. When there is a message which is not considered to be processed and cannot be processed by the FPGA logic, the function is possibly abnormal, and the hang-up is seriously caused. Usually, the unknown messages are all background traffic sent in a normal test scene, and if the FPGA simulation platform is only filled according to the excitation of the test, the problems which can occur in practice cannot be reproduced. Disclosure of Invention In view of the technical problems and defects existing in the prior art, the invention provides an FPGA simulation problem reproduction method based on wireshark packet capturing and time sequence reconstruction by introducing wireshark and FPGA simulation combination, wherein a message sent by opposite terminal equipment is captured on an FPGA by using wireshark, wireshark packet capturing data are injected into an FPGA simulation platform, an actual test scene is truly simulated, and the reproduction rate and positioning efficiency of the FPGA simulation problem are improved. According to a first aspect of the present invention, an FPGA simulation problem reproduction method based on wireshark packet grabbing and timing reconstruction is provided, which includes the following steps: Step 1, in a network environment in which an FPGA actually operates, deploying wireshark tools at a network access node of a DUT (device under test) to capture and store network traffic received and transmitted by the DUT; Step 2, carrying out protocol analysis on the message captured by the wireshark tool, identifying the protocol to which the message belongs according to the protocol configuration file, extracting key fields, classifying the message, identifying and marking the classified message; step 3, screening a message set to be injected according to a preset screening mode, and generating a marked message queue; Step 4, according to the injection mode selected by the user, carrying out time sequence reconstruction on the screened message queue; step 5, generating a transaction in sequencer modules of the UVM simulation platform according to the reconstructed time sequence, converting the transaction into an interface signal of the DUT, and injecting the interface signal into the DUT according to the appointed time sequence; And 6, comparing the expected output of the DUT with the injected output response to obtain simulation r