CN-122021514-A - Novel wafer process SPICE determining method and wafer quality control method

CN122021514ACN 122021514 ACN122021514 ACN 122021514ACN-122021514-A

Abstract

The application relates to the technical field of chip processing, in particular to a method for determining a novel process SPICE of a wafer, which comprises the steps of S110, determining items and characteristic parameters to be tested in the novel process SPICE of the wafer, S120, obtaining target chips in the same process as the novel process of the wafer, obtaining a hierarchical structure of the target chips, S130, sequentially removing the target chips from one side layer by layer, sequentially obtaining target layers of the target chips, positioning the target structure of the items to be tested of the target layers and the target position of the target structure on the target layers, S140, testing by using a nano probe imaging analysis system according to the determined target position, and collecting the characteristic parameters of the target structure, and S150, after the target structures of all the target layers are tested, obtaining the SPICE of the wafer process of the target chips. The method provided by the application can quickly establish SIPCE of a new wafer process, provide a guiding direction for developing the new wafer process, and simultaneously provide a method for quickly obtaining a SPICE test result at low cost.

Inventors

ZHANG QIHUA
ZHANG JIE
JIAN WEITING
XU HONGWEI
Lv Youlong
Request for anonymity

Assignees

洪启集成电路(珠海)有限公司

Dates

Publication Date: 20260512
Application Date: 20251205

Claims (10)

1. The novel wafer process SPICE determining method is characterized by comprising the following steps of: s110, making a test plan, and determining items to be tested in a new wafer process SPICE and characteristic parameters to be acquired in each item; S120, acquiring a target chip with the same process as the new wafer process, acquiring a hierarchical structure of the target chip, and determining the hierarchy of each item according to the item to be tested by the SPICE; s130, removing the target chip layer by layer from one side, sequentially obtaining each target layer of the target chip, positioning a target structure of an item to be tested of the target layer and a target position of the target structure on the target layer every time one target layer is obtained; s140, aiming at each target layer, testing by using a nano probe imaging analysis system according to the determined target position, and collecting characteristic parameters of a target structure; S150, after all target structures of the target layers are tested, SPICE of the target chip wafer process is obtained.
2. The method of claim 1, wherein the step S120 is to obtain a target chip in the same process as the new wafer process, specifically, obtain a target package device in the same process as the new wafer process, and remove the package of the target package device to obtain the target chip of the target package device.
3. The method of claim 2, wherein in the step 120, at least two target packaging devices are obtained, one of the target packaging devices is selected as a first target packaging device, the packaging of the first target packaging device is removed, a first target chip of the first target packaging device is obtained, and a hierarchical structure of the first target chip is obtained; Step 130 includes, removing the first target chip layer by layer from one side, sequentially obtaining each target layer of the first target chip, positioning a target structure of an item to be tested of the target layer, and a target position of the target structure on the target layer; Step 140 includes selecting a second target packaging device as a second target packaging device, removing packaging of the second target packaging device to obtain a second target chip, removing the second target chip layer by layer, and collecting characteristic parameters of the target structure according to the target structure determined in step 130 and the target position of the target structure tested by using a nanoprobe imaging analysis system; the step S150 includes obtaining SPICE of the target chip wafer process after the target structures of all target layers of the second target chip are tested.
4. The method of claim 1, further comprising, after each target layer is obtained and a target structure of the target layer is determined, and a target location of the target structure, the step of performing circuit repair on the target structure using the FIB from the target location to isolate the target structure from the target location.
5. The wafer quality control method is characterized by comprising the following steps: s210, making a test plan, and determining items to be tested for monitoring the quality of the wafer of the new process and characteristic parameters to be acquired for each item; s220, acquiring a target chip with the same process as the new process of the wafer, acquiring a hierarchical structure of the target chip, and determining the hierarchy of each item according to items required to be tested for monitoring the quality of the wafer of the new process; s230, removing the target chip layer by layer from one side, sequentially obtaining each target layer of the target chip, positioning a target structure of an item to be tested of the target layer and a target position of the target structure on the target layer every time one target layer is obtained; S240, aiming at each target layer, testing by using a nano probe imaging analysis system according to the determined target position, and collecting characteristic parameters of a target structure; s250, aiming at different quality control targets, each target structure respectively acquires a preset number of characteristic parameter sets, and a wafer quality control scheme is acquired through calculation.
6. The method according to claim 5, wherein the step S250 is specifically: Aiming at a quality control scheme in a chip, searching a preset number of similar structures for each target structure on the same chip, respectively measuring by using a nano probe imaging analysis system to obtain a preset number of data sets, calculating an average value and a variance by using a statistical method, and calculating the quality control scheme; aiming at a quality control scheme among the chips with the same function, obtaining a preset number of target chips, searching target structures with the same structure on each target chip, respectively measuring by using a nanoprobe imaging analysis system to obtain a preset number of data sets, calculating an average value and a variance by using a statistical method, and calculating the quality control scheme; For the quality control schemes of different functional chips, a preset number of different functional target chips are obtained, target structures with similar structures are found on each target chip, measurement is respectively carried out by using a nanoprobe imaging analysis system, a preset number of data sets are obtained, a statistical method is used for calculating the average value and the variance, and the statistical method is used for calculating the quality control scheme.
7. The method of claim 6, wherein in the step 220, at least two target packaging devices are obtained, one of the target packaging devices is selected as a first target packaging device, the packaging of the first target packaging device is removed, a first target chip of the first target packaging device is obtained, and a hierarchical structure of the first target chip is obtained; step 230 includes, removing the first target chip layer by layer from one side, sequentially obtaining each target layer of the first target chip, positioning a target structure of an item to be tested of the target layer, and a target position of the target structure on the target layer; Step 240 includes selecting a second target packaging device as a second target packaging device, removing packaging of the second target packaging device to obtain a second target chip, removing the second target chip layer by layer, and collecting characteristic parameters of the target structure according to the target structure determined in step 230 and the target position of the target structure tested by using a nanoprobe imaging analysis system; The step 250 specifically includes: Aiming at a quality control scheme in a chip, on the second target chip, searching a preset number of similar structures for each target structure, respectively measuring by using a nano probe imaging analysis system to obtain a preset number of data sets, calculating an average value and a variance by using a statistical method, and calculating the quality control scheme; Aiming at a quality control scheme among the chips with the same function, acquiring a preset number of second target chips, and repeating the step S240 for each second target chip, so as to find target structures with the same structure on each second target chip, respectively measuring by using a nanoprobe imaging analysis system to acquire a preset number of data sets, calculating an average value and a variance by using a statistical method, and calculating the quality control scheme; and (3) aiming at the quality control schemes of the chips with different functions, acquiring a preset number of second target chips with different functions, and repeating the step S240 for each second target chip, so as to find target structures with similar structures on each second target chip, respectively measuring by using a nanoprobe imaging analysis system to acquire a preset number of data sets, calculating the average value and the variance by using a statistical method, and calculating the quality control scheme.
8. The method of claim 7, further comprising, after each target layer is obtained and a target structure of the target layer is determined, and a target location of the target structure, the step of performing circuit repair on the target structure using the FIB from the target location to isolate the target structure from the target location.
9. An electronic device comprising a memory storing a computer executable program and a processor invoking the computer executable program in the memory to perform the method of any of claims 1-8.
10. A storage medium, characterized in that the storage medium is a computer-readable storage medium, on which a computer-executable program is stored, which computer-executable program, when being executed by a processor, implements the method according to any one of claims 1to 8.

Description

Novel wafer process SPICE determining method and wafer quality control method Technical Field The invention relates to the technical field of chip processing, in particular to a novel wafer process SPICE determining method and a wafer quality control method. Background PDK (Process DESIGN KIT ) is an important concept in the field of integrated circuit design, and is an indispensable bridge for connecting chip design and semiconductor manufacturing processes. The PDK provides design rules, physical layer parameters and verification files related to a specific wafer process, so that the designed chip can realize expected performance in a wafer factory process. The PDK contains the following key files: ‌ design rules ‌ defining physical limits such as minimum linewidth and spacing of geometric figure, ensuring physical layout to meet manufacturing limit of specific process node, ensuring producibility, ‌ ‌ Device model ‌ SPICE model providing devices such as transistors, resistors, capacitors, etc., for simulation prediction of circuit performance, ‌ ‌ A layout parameterization unit ‌, which is used for providing a pre-verified device template and simplifying the design flow; ‌ physical verification rules ‌ ensure consistency of the layout and the schematic diagram, and avoid manufacturing risks. ‌ A The PDK, particularly the device model (SPICE model), is a basic data that each wafer factory needs to provide to an internal customer (design department or design provider) or an external customer (IP provider or design company) when developing a new process or product. However, PDK is a highly confidential material for wafer manufacturers, and is subject to the highest level of security management to prevent competitors from obtaining it. When developing PDKs, wafer manufacturers typically require SPICE in four stages: The new process design stage (T0) is that when a new process is developed, since Testkey (test structure/unit device), TQV (Technology Qualification Vehicle, technical identification vehicle) and PQV (Product Qualification Vehicle, product identification vehicle) are not yet made, the method for providing SPICE (V0X) comprises the following steps of calculating theoretical values based on theoretical calculation, such as square resistance (Rs) of an AA layer, MOS tube saturation current (Idsat) with a specific size and the like, according to data collected by a previous generation process or other process platforms of the same generation and combining physical principles; The new Process development stage (T1) is determined by the first Process (Process) of the stage, and the basic Testkey, TQV, PQV and the like are designed, and the wafer flows out of the first batch of wafers. SPICE (V1X) can be obtained after testing various test structures by a tester: The new process is completed in stage (T2) which has run out a large number of batches of wafers from the wafer. By constantly optimizing the process and test structures. A large amount of data can be obtained after various test structures are tested by a tester, and SPICE (V2X) is perfected; The new process mass production stage (T3) is that when the process is completed and used for manufacturing products of various customers, the problem of low yield is encountered, and the process is required to be locally modified at this time to improve the yield, and then a new SPICE (V3X) corresponding to the specific product or process is generated. In the above-mentioned stages, especially from the T0 stage to the T1 stage, the theoretical calculation result and the actual measurement value are quite different, and the target specification is quite different, so that the process needs to be continuously adjusted and optimized according to the target specification. Therefore, this stage is time consuming and costly for the wafer manufacturer. On the other hand, in the process of developing a new process, if a certain SPICE important parameter cannot be collected due to planned missing, if a normal SPICE model data collection method is used, a whole set of work such as design of a test structure, flow sheet, test program writing, design and manufacture of a test chuck and the like is needed, so that time and labor are consumed, and a more flexible SPICE technology for acquiring a new process flow is also expected. Disclosure of Invention Based on the problems of the prior art, the embodiment of the application provides a method for determining a novel process SPICE of a wafer, which can accelerate the rapid research and development of the novel process SPICE of wafer manufacturers in China in the position of wafer manufacturers for a long time, and accelerate the time for inputting the novel process into mass production, thereby accelerating the speed of catching up with advanced process on one hand, and reducing the cost for developing the novel process on the other hand, and has great engineering value. Meanwhile, a flexible low-cost acquisition metho