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CN-122021516-A - Ethernet circuit and design method

CN122021516ACN 122021516 ACN122021516 ACN 122021516ACN-122021516-A

Abstract

The invention discloses an Ethernet circuit and a design method thereof, wherein the circuit comprises an Ethernet PHY chip, an Ethernet connector, hundred mega and giga Ethernet communication branches, the hundred mega branches are connected in series with a first common mode choke coil, a first common mode terminal circuit and a first vehicle-mounted connector and distributed on the bottom layer of a PCB, the giga branches are connected in series with a second common mode choke coil, a second common mode terminal circuit and a second vehicle-mounted connector and distributed on the top layer of the PCB, the circuits of the giga branches extend to the bottom layer through water drop type connection and punching, symmetrical through holes are arranged at two sides of the punching, the two branches share the same pair of pins of the PHY chip and the connector, and the two branches are configured to be independently referenced and shielded with the same layer. According to the invention, the independent dedicated common mode choke coil and the common mode terminal circuit are respectively configured for hundred megabytes and gigabit Ethernet communication branches, so that the problem that different speed filter devices cannot be commonly used due to large frequency characteristics and packaging differences is radically avoided without forced sharing of filter devices, and the stability of the communication performance of each speed is ensured.

Inventors

  • WANG XIUTIAN

Assignees

  • 奇瑞汽车股份有限公司

Dates

Publication Date
20260512
Application Date
20260121

Claims (10)

  1. 1. An electrical circuit for an ethernet network is provided, characterized by comprising the following steps: an Ethernet PHY chip (1), an Ethernet connector (8), a hundred megaEthernet communication branch and a gigabit Ethernet communication branch; The hundred megaEthernet communication branch is sequentially connected with a first common mode choke coil (2), a first common mode terminal circuit (3) and a first vehicle-mounted connector (4) in series along the signal transmission direction, the transmission line of the hundred megaEthernet communication branch is arranged on the bottom layer of the PCB, and two ends of the hundred megaEthernet communication branch are respectively and electrically connected to the same pair of pins of the Ethernet PHY chip (1) and the same pair of pins of the Ethernet connector (8); The gigabit Ethernet communication branch is sequentially connected with a second common mode choke coil (5), a second common mode terminal circuit (6) and a second vehicle-mounted connector (7) in series along the signal transmission direction, the transmission line of the gigabit Ethernet communication branch is arranged on the top layer of the PCB, and two ends of the gigabit Ethernet communication branch are correspondingly and electrically connected to the same pair of pins of the Ethernet PHY chip (1) and the same pair of pins of the Ethernet connector (8); after the transmission line of the gigabit Ethernet communication branch is led out from the pin of the Ethernet PHY chip (1), the transmission line is transited by a water drop type connecting line and extends to the bottom layer of the PCB through punching, and through holes are symmetrically arranged on two sides of the punching; Wherein, hundred megaEthernet communication branch and giga Ethernet communication branch dispose independent reference ground and same layer shielding ground respectively.
  2. 2. An ethernet circuit according to claim 1, wherein pins of said ethernet connector (8) are through-hole pin structures penetrating the PCB, said through-hole pin structures forming electrical connection terminals on the top and bottom layers of the PCB, respectively; The transmission line of the gigabit Ethernet communication branch is electrically connected with the electrical connection end of the through hole pin structure positioned on the top layer of the PCB; and the transmission line of the hundred-mega Ethernet communication branch is electrically connected with the electric connection end of the through hole pin structure positioned at the bottom layer of the PCB.
  3. 3. An ethernet circuit according to claim 1, wherein in the gigabit ethernet communication branch, the second common mode choke (5) and the resistive element of the second common mode termination circuit (6) are integrated on the top layer of the PCB in a coplanar manner, and are sequentially arranged and electrically connected along the signal flow direction of the branch transmission line; In the hundred-mega Ethernet communication branch, the first common mode choke coil (2) and the resistance element of the first common mode terminal circuit (3) are integrated on the bottom layer of the PCB, and the first common mode choke coil and the resistance element of the first common mode terminal circuit are sequentially distributed along the signal flow direction of the branch transmission line to form electric connection.
  4. 4. An ethernet circuit according to claim 1, wherein the radius of curvature of said drop-type connection is adapted to the aperture parameters of said holes, and said holes are symmetrically arranged on both sides of said holes, each of which is equal to the center-to-center distance of said holes.
  5. 5. An ethernet circuit design method for designing an ethernet circuit as claimed in any one of claims 1 to 4, comprising: Multiplexing the transmission line of the hundred megaEthernet communication branch with the transmission line of the gigabit Ethernet communication branch, multiplexing the same pair of pins of the same Ethernet connector and connecting the same pair of pins of the same Ethernet PHY chip, and realizing the sharing of the pins of the Ethernet connector and the pins of the Ethernet PHY chip by the two branches; when the transmission line of the gigabit Ethernet communication branch is arranged on the top layer of the PCB, punching the transmission line to extend to the bottom layer of the PCB in a water drop type connection mode at the pin outlet position of the Ethernet PHY chip, and symmetrically arranging through holes at two sides of the punching to maintain the continuity of the ground impedance of the transmission line; Arranging transmission lines of the hundred-mega Ethernet communication branches on the bottom layer of the PCB, and enabling the transmission lines of the two branches to be arranged independently of each other by utilizing the structural characteristic that pins of an Ethernet connector penetrate through the PCB; the method comprises the steps that corresponding reference ground and same-layer shielding ground are respectively and independently distributed for a transmission line of a hundred megaEthernet communication branch and a transmission line of a gigabit Ethernet communication branch; Respectively carrying out impedance continuity simulation on the transmission line of the hundred mega Ethernet communication branch and the transmission line of the gigabit Ethernet communication branch, so that the total link impedance of the two transmission lines is kept at about 100 ohms; S parameter simulation is carried out on a transmission line of a hundred-megaEthernet communication branch and a transmission line of a gigabit Ethernet communication branch, wherein the S parameter simulation at least comprises insertion loss simulation, return loss simulation and conversion loss simulation, so that the two transmission lines can meet the physical layer specification requirements of the Open Alliance.
  6. 6. The ethernet circuit design method according to claim 5, further comprising, after the transmission line of the gigabit ethernet communication branch is arranged on the top layer of the PCB: and the second common mode choke corresponding to the branch and the resistance element of the second common mode terminal circuit are arranged on the top layer of the PCB in a coplanar manner.
  7. 7. The method for designing an ethernet circuit according to claim 5, further comprising, after the transmission lines of said hundred mega ethernet communication leg are routed on the PCB substrate: and uniformly distributing the first common mode choke coil corresponding to the branch and the resistance element of the first common mode terminal circuit on the bottom layer of the PCB.
  8. 8. The Ethernet circuit design method as set forth in claim 5, wherein, When the transmission line of the hundred-megaethernet communication branch is used for multiplexing the operation of the same pair of pins of the same Ethernet connector with the transmission line of the gigabit ethernet communication branch, the hundred-megaethernet communication branch is designed based on an IEEE 802.3bw protocol, and the gigabit ethernet communication branch is designed based on the IEEE 802.3bp protocol.
  9. 9. The method for designing an ethernet circuit according to claim 5, wherein the physical layer specification requirements of the Open Alliance are satisfied by both transmission lines, specifically: The S parameter simulation result needs to ensure that the Signal Quality Index (SQI) and the Bit Error Rate (BER) of line transmission meet the corresponding specification requirements.
  10. 10. The method for designing an ethernet circuit according to claim 5, further comprising: And performing software configuration on the Ethernet PHY chip through the MCU to realize the noninductive switching of the hundred megabytes Ethernet communication branch and the gigabit Ethernet communication branch.

Description

Ethernet circuit and design method Technical Field The invention belongs to the technical field of automatic driving Ethernet circuit design, and particularly relates to an Ethernet circuit and a design method. Background The existing ethernet circuit design has significant defects, specifically, different-rate ethernet (such as hundred mega and giga ethernet) cannot share a filter device, which becomes a core bottleneck of hardware design, and the core cause of the defects is that the frequency characteristic of the filter device (specifically including common-mode inductance CMC and an ethernet protocol dedicated termination filter circuit CM termination) is strongly related to the rate, and the packaging difference of the filter device corresponding to different frequency bands is extremely large, so that the filter device cannot be used for trans-rate application. The reasons directly cause multiple defects, firstly, when the circuit schematic diagram, the BOM list and the circuit board layout wiring are required to be redeveloped and simulation verification of a new layout is required to be additionally carried out during adaptation of different customer rate requirements, the research and development period is greatly prolonged and the research and development cost is increased, and secondly, in order to reserve the multi-rate expansion capability, the industry usually adopts a multi-port Ethernet switch chip, the cost of the multi-port Ethernet switch chip is equivalent to or even higher than that of an MCU chip, the area of the circuit board is increased, and the unit price of the circuit board and the whole BOM cost are further increased. Finally, these problems seriously hinder the progress of hardware platform, which makes it difficult for enterprises to quickly respond to customer demands, and restricts the efficient iteration and development of the industry. Disclosure of Invention The invention aims to provide an Ethernet circuit and a design method thereof, which are used for solving the technical defect that in the prior art, different circuits are required to be designed when different speed demands are faced because different speed Ethernet cannot share a filter device. In order to achieve the above purpose, the invention is realized by adopting the following technical scheme: in a first aspect of the application, an ethernet circuit is provided, comprising: An ethernet PHY chip, an ethernet connector, a hundred mega ethernet communication leg, and a gigabit ethernet communication leg; The hundred megaEthernet communication branch is sequentially connected with a first common mode choke coil, a first common mode terminal circuit and a first vehicle-mounted connector in series along the signal transmission direction, the transmission line of the hundred megaEthernet communication branch is arranged on the bottom layer of the PCB, and two ends of the branch are respectively and electrically connected to the same pair of pins of the Ethernet PHY chip and the same pair of pins of the Ethernet connector; the gigabit Ethernet communication branch is sequentially connected with a second common mode choke coil, a second common mode terminal circuit and a second vehicle-mounted connector in series along the signal transmission direction, the transmission line of the gigabit Ethernet communication branch is arranged on the top layer of the PCB, and two ends of the branch are correspondingly and electrically connected to the same pair of pins of the Ethernet PHY chip and the same pair of pins of the Ethernet connector; After the transmission line of the gigabit Ethernet communication branch is led out from the pins of the Ethernet PHY chip, the transmission line is transited by a water drop type connecting line and extends to the bottom layer of the PCB through punching, and through holes are symmetrically arranged on two sides of the punching; Wherein, hundred megaEthernet communication branch and giga Ethernet communication branch dispose independent reference ground and same layer shielding ground respectively. In an alternative embodiment, pins of the ethernet connector adopt a through hole pin structure penetrating through the PCB, and the through hole pin structure forms electrical connection ends on the top layer and the bottom layer of the PCB respectively; The transmission line of the gigabit Ethernet communication branch is electrically connected with the electrical connection end of the through hole pin structure positioned on the top layer of the PCB; and the transmission line of the hundred-mega Ethernet communication branch is electrically connected with the electric connection end of the through hole pin structure positioned at the bottom layer of the PCB. In an alternative embodiment, in the gigabit ethernet communication branch, the second common mode choke and the resistive element of the second common mode termination circuit are integrated on the top layer of the PCB in a coplanar