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CN-122021521-A - Two-dimensional Ising model evolution simulation circuit based on threshold voltage type memristor

CN122021521ACN 122021521 ACN122021521 ACN 122021521ACN-122021521-A

Abstract

The invention discloses a two-dimensional Ising model evolution simulation circuit based on a threshold voltage type memristor, which belongs to the technical field of microelectronics, is used for simulating the evolution process of a two-dimensional Ising model, comprises a plurality of Ising nodes which are arranged in an M-row N-column array, a plurality of Ising node coupling circuits which are in one-to-one correspondence with the Ising nodes, a random bit stream generator, a power supply terminal VCC, VDD, VEE, GND, a signal INPUT terminal U_CLK, U_RESET and U_INPUT_EN, and has the advantages of high speed of spin state storage and miniaturization of the circuit, accurate energy calculation, clear state inversion control logic, capability of efficiently simulating the evolution process of the two-dimensional Ising model, and providing reliable core circuit support for the design of the Ising machine, and improvement of the accuracy and stability of evolution simulation.

Inventors

  • GAN CHAOHUI
  • FANG XINGJIE

Assignees

  • 武汉科技大学

Dates

Publication Date
20260512
Application Date
20251209

Claims (8)

  1. 1. The two-dimensional Ising model evolution simulation circuit based on the threshold voltage type memristor is characterized by being used for simulating the evolution process of a two-dimensional Ising model and comprising a plurality of Ising nodes which are arranged in an array of M rows and N columns, a plurality of Ising node coupling circuits which are in one-to-one correspondence with the Ising nodes, a random bit stream generator, a power supply terminal VCC, VDD, VEE, GND, a signal INPUT terminal U_CLK, U_RESET, U_INPUT_EN, U_ASSIGN, U_SELECT_ODD, U_SELECT_EVEN, an M_INPUT_SIG_1-1 to U_INPUT_SIG_M-N, 2M+2N 16-bit signal INPUT terminals U_RNG_SIG_1 [15:0] to U_RNG_ING_2N [15:0], a 16-bit signal INPUT terminal U_RNG_d8_th [15:0], a 16-bit signal INPUT terminal U_SIG_1-1 to U_ING_SIG_1 [15:0] and an array of the two-dimensional Ising nodes, wherein the array of the two-dimensional Ising nodes represents that the number of the two-dimensional Ising model evolution simulation circuit is that the two-dimensional Ising model is arranged in the array of M rows and N columns of the two-dimensional Ising nodes; The signals input by the terminals U_ASSIGN, U_ SELEGT _ODD and U_SELECT_EVEN are used for controlling all the Ising node states to be updated alternately, the Ising node coupling circuit calculates the energy change delta E of the two-dimensional Ising model based on the corresponding Ising node states and the neighbor Ising node states, controls the corresponding Ising node to overturn according to the Metropolis criterion according to the corresponding two-bit random bit values generated by the random bit stream generator, and completes simulation of the evolution process of the two-dimensional Ising model after multiple evolution, wherein the neighbor Ising node states represent the upper, lower, left and right 4 neighbor Ising node states.
  2. 2. The two-dimensional Ising model evolution simulation circuit of claim 1, wherein the Ising node comprises a first memristor cell, a second memristor cell, a first gate, a terminal RST, a terminal ASSIGN, a terminal SELECT, a terminal REVERSE, and a terminal STATE, the first memristor cell comprises a first threshold voltage type memristor, a first numerical control switch, a first current mirror, a first inverter, a second inverter, a first resistor, a second resistor, a first NMOS, the first PMOS and the second PMOS, the M1 end of the first threshold voltage type memristor is connected with a VDD power supply through the first resistor, the M1 end of the first threshold voltage type memristor is also connected with one end of the first numerical control switch and the drain electrode of the second PMOS respectively, the other end of the first numerical control switch is connected with the drain electrode of the first NMOS and the drain electrode of the first PMOS respectively, the source electrode of the first NMOS is connected with a VEE power supply, the source electrode of the first PMOS is connected with a VCC power supply, the source electrode of the second PMOS is connected with a VCC power supply, the M2 end of the first threshold voltage type memristor is connected with a first current mirror input end, the output end of the first current mirror is connected with a RST terminal through the second resistor and drives the second inverter, the output end of the first inverter is connected with the grid electrode of the second PMOS, the first numerical control switch control end is connected with an ASGN terminal, and the second memristor comprises a second threshold voltage type memristor, a second digital control switch, a second current mirror, a third inverter, a fourth inverter, a third resistor, a fourth resistor, a second NMOS, The third PMOS and the fourth PMOS, the M1 end of the second threshold voltage type memristor is connected with a VDD power supply through the third resistor, the M1 end of the second threshold voltage type memristor is also respectively connected with one end of the second digital control switch and the drain of the fourth PMOS, the other end of the second digital control switch is respectively connected with the drain of the second NMOS and the drain of the third PMOS, the source of the second NMOS is connected with a VEE power supply, the source of the third PMOS is connected with a VCC power supply, the source of the fourth PMOS is connected with a VCC power supply, the M2 end of the second threshold voltage type memristor is connected with a second current mirror input end, the output end of the second current mirror is connected with a VCC power supply through the fourth resistor and drives the third inverter, the output end of the third inverter is connected with the input end of the fourth inverter, the output end of the first inverter is connected with the grid of the fourth PMOS, the second digital control switch control end is connected with the VEE power supply, the source of the third PMOS is connected with the second PMOS, the output end of the second inverter is connected with the first grid of the fourth inverter is connected with the first gate of the fourth inverter, the output end of the second inverter is connected with the fourth inverter is connected with the output end of the fourth inverter is connected with the gate of the third inverter, and the gate of the fourth inverter is connected with the gate of the fourth inverter is respectively.
  3. 3. The two-dimensional Ising model evolution simulation circuit of claim 1, wherein the Ising node coupling circuit comprises an energy calculation unit and a flip control unit, INPUT terminals UP_STATE, DOWN_STATE, LEFT_STATE, RIGHT_STATE, MID_STATE, INPUT_EN, INPUT_ SIG, SELECT, PROB _dE4, PROB_dE8 and an output terminal REVERSE, wherein UP_STATE of the i-j th Ising node coupling circuit, DOWN_STATE, LEFT_STATE, RIGHT_STATE terminals and the ((i-1) mod N) -j, ((i+1) mod N) -j, i- ((j-1) mod N), The STATE terminals of the i- ((j+1) mod N) Ising node are respectively connected, i is an integer from 1 to M, j is an integer from 1 to N, the MID_STATE terminal is connected with the STATE terminal of the Ising node corresponding to the Ising node coupling circuit, and delta E after the Ising node corresponding to the Ising node coupling circuit is turned over is calculated according to a formula delta E= -2.S ij ·Σ(S neighbor ), wherein S ij represents the STATE of the spin in the j-th row in the two-dimensional Ising model, S neighbor represents the STATE of the spin adjacent to the spin in the j-th row in the two-dimensional Ising model, and when delta E is four, the first energy STATE indicating signal dE4_EN is high level, The second energy state indication signal dE8_EN is high when ΔE is eight, the flip control unit updates the state of the terminal REVERSE according to the signals dE4_EN, dE8_EN, the signals of the terminals SELECT, PROB_dE4, PROB_dE8, INPUT_EN and INPUT_SIG, thereby controlling whether the corresponding Ising node performs state flip, when the signal of the terminal SELECT is high, if the terminal INPUT_EN, When the signal of input_sig is at high level at the same time, the terminal REVERSE outputs high level, otherwise outputs low level, when the signal of the terminal input_en is at low level, if the signal of the signal de4_en and the signal of the terminal prob_de4 are at high level at the same time, or the signal of the signal de8_en and the signal of the terminal prob_de8 are at high level at the same time, or the signals de4_en and de8_en are at low level at the same time, the terminal REVERSE outputs high level, otherwise the terminal REVERSE outputs low level, when the signal of the terminal SELECT is at low level, the terminal REVERSE outputs low level.
  4. 4. The two-dimensional Ising model evolution simulation circuit of claim 1, wherein for an array of Ising nodes of M rows and N columns, the random bit stream generator comprises 2M+2N random bit generator units, 2 XM N two-INPUT AND gate units, one INPUT terminal RNG_CLK, one INPUT terminal RNG_RESET, one INPUT terminal RNG_INPUT_EN, 2M+2N 16-bit INPUT terminals RNG_INPUT_SIG_1[15:0] to RNG_INPUT_SIG_2M+2N [15:0], and the like, A 16-bit input terminal RNG_dE8_th [15:0], a 16-bit input terminal RNG_dE4_th [15:0] An M×N bit output terminal PROB_dE8_1-1 to PROB_dE8_M-N AND an M×N bit output terminal PROB_dE4_1-1 to PROB_dE4_M-N, said INPUT terminal RNG_CLK being connected to terminals RNG_Unit_CLK of 2M+2N said random bit generator units, said INPUT terminal RNG_RESET being connected to terminals RNG_Unit_RESET of 2M+2N said random bit generator units, said INPUT terminal RNG_INPUT_EN being connected to terminals RNG_INPUT_EN of 2M+2N said random bit generator units, said INPUT terminals RNG_INPUT_SIG_1[15:0] to RNG_INT_2M+2N [15:0] being connected to G_INT_INT_15:0 ] terminals of the 1 st to 2M+2N said random bit generator units, respectively, the output terminals PROB_dE8-1 to PROB_dE8_M-N are respectively connected with the PROB_dE8 terminals of the 1-1Ising node coupling circuit to the M-NIsing node coupling circuit, the output terminals PROB_dE4_1 to PROB_dE4_M-N are respectively connected with the PROB_dE4 terminals of the 1-1Ising node coupling circuit to the M-NIsing node coupling circuit, M x N AND gates in 2 x M x N two INPUT AND gate units form an M row N column AND gate array Part_AND_dE8, M x N AND gates form an M row N column AND gate array Part_AND_dE4, 16 bit terminals RNG_dE8_th [15:0] of the random bit stream generator are respectively connected with 16 bit INPUT terminals G_Unit [15:0] of the 1 st random bit generator Unit to M+N random bit generator Unit, the output ends PROB_Unit of the 1 st to M th random bit generator units are respectively connected with the first input ends of the 1 st to M th N AND gates in the PART_AND_dE8, AND the output ends PROB_Unit of the M+1 th to M+N random bit generator units are respectively connected with the second input ends of the 1 st to N M AND gates in the PART_AND_dE8; the 16 bit terminals RNG_dE4_th [15:0] of the random bit stream generator are correspondingly connected with the 16 bit input terminals RNG_Unit_th [15:0] of the M+N+2N random bit generator units to 2M+N random bit generator units, the output ends PROB_Unit of the M+N+N random bit generator units to 2M+N random bit generator units are respectively connected with the first input ends of the 1 st row N AND gates to the M row N AND gates in the PART_AND_dE4, the output ends PROB_Unit of the 2M+N+1 random bit generator units to 2M+2N random bit generator units are respectively connected with the second input ends of the M AND gates from the 1 st column to the N th column in the PART_AND_dE4, the output ends of the M AND gates from the 1 st row to the M row in the PART_AND_dE8 are respectively connected with the output terminals PROB_dE8_1-1 to PROB_dE8_M-N of the random bit stream generator, AND the output ends of the M AND gates from the 1 st row to the M row in the PART_AND_dE4 are respectively connected with the output terminals PROB_dE4_1-1 to PROB_dE4_M-N of the random bit stream generator.
  5. 5. The two-dimensional Ising model evolution simulation circuit according to claim 4, wherein the random bit generator unit comprises a 16-bit linear feedback shift register and a 16-bit digital comparator, wherein the 16-bit linear feedback shift register comprises a cascade of a first D flip-flop to a sixteenth D flip-flop, a ninth AND gate to a twenty-fourth AND gate, a sixth XOR gate, a seventh XOR gate, an eighth XOR gate, an INPUT terminal CLK, an INPUT terminal RESET, an INPUT terminal INPUT_EN, A 16-bit INPUT terminal INPUT_SIG [15:0] and a 16-bit OUTPUT terminal OUTPUT [15:0], the INPUT terminal CLK is connected with the RNG_Unit_CLK terminal of the random bit generator Unit, the INPUT terminal RESET is connected with the RNG_Unit_RESET terminal of the random bit generator Unit, the INPUT terminal INPUT_EN is connected with the RNG_Unit_INPUT_EN terminal of the random bit generator Unit, the 16-bit INPUT terminal INPUT_SIG [15:0] is connected with the RNG_INPUT_SI G [15:0] terminal of the random bit generator Unit respectively, the first to sixteenth D flip-flops are connected in series in sequence, the OUTPUT terminals of the ninth to twenty-fourth AND gates are connected with the set terminals of the first to sixteenth D flip-flops respectively, the two INPUT terminals of the sixth exclusive OR gate are connected with the OUTPUT terminals of the eleventh D flip-flop and the seventh exclusive OR gate respectively, the OUTPUT end of the sixth exclusive-or gate is connected with the INPUT end of the first D trigger, the two INPUT ends of the seventh exclusive-or gate are respectively connected with the OUTPUT end of the thirteenth D trigger and the OUTPUT end of the eighth exclusive-or gate, the two INPUT ends of the eighth exclusive-or gate are respectively connected with the OUTPUT ends of the fourteenth D trigger and the sixteenth D trigger, the clock ends of the first D trigger to the sixteenth D trigger are respectively connected with the CLK terminal, the RESET ends of the first D trigger to the sixteenth D trigger are respectively connected with the RESET terminal, the first INPUT ends of the ninth AND gate to the twenty-fourth AND gate are respectively connected with the INPUT_EN terminal, the second INPUT ends of the ninth AND gate to the twenty-fourth AND gate are respectively connected with the 16-bit INPUT terminal INPUT_SI G [15:0], the OUTPUT ends of the first D trigger to the sixteenth D trigger are respectively connected with 16-bit OUTPUT terminals OUTPUT [15:0] of the linear feedback shift register, and the 16-bit digital comparator comprises a 16-bit input terminal A [15:0] The OUTPUT terminal B [15:0] is correspondingly connected with the input terminal A [15:0], the OUTPUT terminal B [15:0] is respectively connected with the input terminal RNG_Unit_th [15:0] of the random bit generator Unit, the OUTPUT terminal OUT is connected with the OUTPUT terminal PROB_Unit of the random bit generator Unit, and if the numerical value of a digital signal input by the input terminal A [15:0] is larger than that of a digital signal input by the input terminal B [15:0], the OUTPUT terminal OUT OUTPUTs a high level, and otherwise, the OUTPUT terminal OUT OUTPUTs a low level.
  6. 6. The two-dimensional emission model evolution simulation circuit according to claim 1, wherein the terminals U_SELECT_ODD, U_SELECT_EVEN and U_ASSIGN are used for controlling all emission nodes to update alternately according to a chessboard algorithm so as to simulate the evolution process of the emission model, the emission nodes and the coupling circuits thereof are divided into ODD nodes and EVEN nodes according to parity of the sum of row and column numbers i and j of the emission nodes, the U_SELECT_ODD terminal is connected with the SELECT terminals of all ODD nodes, the U_SELECT_EVEN terminal is connected with the SELECT terminals of all EVEN nodes, the update of the emission nodes is performed in three periods, the U_SELECT_ODD terminal outputs a high level in a first period, the U_SELECT_ODD terminal outputs a low level, the U_ASSIGN terminal outputs a low level in a second resistance update state of all ODD nodes, the U_SELECT_ODD terminal is connected with the second resistance update state, the U_SELECT_ODD terminal is connected with the second resistance unit, and the U_SELECT_ODD terminal is simultaneously, and the U_ASSIGN_ODD terminal is simultaneously stopped in a two-dimensional state, and the U_ASSIGN_ODD terminal is simultaneously, and the two-dimensional state of the two-dimensional emission model is simultaneously simulated, and the two-dimensional emission model is completely.
  7. 7. The two-dimensional Ising model evolution simulation circuit according to claim 1, wherein: the power supply terminal VCC is connected with a VCC power supply of the two-dimensional Ising model evolution analog circuit, the power supply terminal VDD is connected with a VDD power supply of the two-dimensional Ising model evolution analog circuit, the power supply terminal VEE is connected with a GND of the two-dimensional Ising model evolution analog circuit, the U_CLK terminal is connected with an RNG_CLK terminal of the random bit stream generator and is used for providing clocks for a 16-bit linear feedback shift register in the random bit stream generator, the U_RESET terminal is connected with a RST terminal of all the Ising nodes and an RNG_RESET terminal of the random bit stream generator, when the U_RESET terminal OUTPUTs high level, all first threshold voltage type memristors and second threshold voltage type memristors of all the Ising nodes are set to be in a low resistance state, 16-bit OUTPUT ends OUUT [15:0] of all the 16-bit linear feedback shift registers in the random bit stream generator are connected with a low-level OUTPUT terminal while rising, the U_RESET terminal is connected with the two-dimensional INPUT terminal of the random bit stream generator and the two-dimensional INPUT terminal 1-bit stream generator, the two-bit stream generator is coupled with the initial terminal 1-bit stream control terminal of the two-dimensional INPUT model INPUT terminal 1, the initial state INPUT terminal is connected with the two-dimensional INPUT terminal 1, and the initial state 1is connected with the initial state of the OUTPUT terminal 1, the U_RNG_INPUT_SIG_1[15:0] terminals to U_RNG_INPUT_SIG_2M+2N [15:0] terminals are connected to RNG_INPUT_SIG_1[15:0] terminals to RNG_INPUT_SIG_2M+2N [15:0] terminals of the random bit stream generator, respectively, external signals INPUT from the terminals are used to set initial values of all the 16-bit linear feedback shift registers in the random bit stream generator, the U_RNG_dE8_th [15:0] terminals and U_RNG_dE4_th [15:0] terminals are connected to RNG_dE8_th [15:0] terminals and RNG_dE4_th [15:0] terminals of the random bit stream generator circuit, respectively, the external signals INPUT from the terminals are used for setting the temperature parameters of the two-dimensional Ising model simulated by the two-dimensional Ising model evolution simulation circuit, the STATE terminals from the 1-1Ising node to the M-N Ising node are respectively connected with the STATE_1-1 terminal to the STATE_M-N terminal of the two-dimensional Ising model evolution simulation circuit, and the STATE of the signals output from the terminals is the spin STATE of the two-dimensional Ising model simulated by the circuit.
  8. 8. The two-dimensional Ising model evolution simulation circuit according to claim 1, wherein the voltage of the power supply terminal VCC is 3V, the voltage of the power supply terminal VDD is 2V, the voltage of the power supply terminal GND is 0V, and the voltage of the power supply terminal VEE is-3V.

Description

Two-dimensional Ising model evolution simulation circuit based on threshold voltage type memristor Technical Field The invention relates to the technical field of microelectronics, in particular to a two-dimensional Ising model evolution simulation circuit based on a threshold voltage type memristor. Background The two-dimensional Ising model is a classical model for researching spin interaction in a magnetic material, in numerical solution calculation, a Monte Carlo method, particularly a Metropolis algorithm is generally adopted, the spin direction of each lattice point is randomly initialized on a two-dimensional lattice, then one lattice point is randomly selected according to the Metropolis criterion, the energy change after spin turnover is calculated, if the energy is reduced, the spin turnover is accepted, if the energy is increased, the spin turnover is accepted with a certain probability, the system gradually reaches a thermal equilibrium state through a large number of iterations, and at the moment, the physical quantities such as the magnetic susceptibility, the specific heat capacity and the like of the spin are counted. In the prior art, circuits for simulating the evolution of a two-dimensional Ising model mostly adopt SRAM or registers to store spin states, and when the SRAM is adopted for storage, the problems of complex operation steps and low evolution efficiency exist, and when the registers are adopted for storage, the reading and writing speeds are higher, but the required circuit scale is large, the hardware cost is high, both modes are difficult to consider optimization of the evolution efficiency and the circuit area, and the integration and the practicability of the Ising model simulation circuit are limited. Disclosure of Invention The invention aims to provide a two-dimensional Ising model evolution simulation circuit based on a threshold voltage type memristor, which aims to solve the technical problems of complex operation steps, low evolution efficiency and high circuit scale and hardware overhead when using a register for storage in the prior art when adopting SRAM for storage. The invention provides a two-dimensional Ising model evolution simulation circuit based on a threshold voltage type memristor, which is used for simulating the evolution process of a two-dimensional Ising model and comprises a plurality of Ising nodes which are arranged in an M-row N-column array, a plurality of Ising node coupling circuits which are in one-to-one correspondence with the Ising nodes, a random bit stream generator, a power supply terminal VCC, VDD, VEE, GND, a signal INPUT terminal U_CLK, U_RESET, U_INPUT_EN, U_ASSIGN, U_SELECT_ODD, U_SELECT_EVEN, an M x N bit signal INPUT terminal U_INPUT_SIG_1-1 to U_INPUT_SIG_M-N, 2M+2N 16 bit signal INPUT terminals U_RNG_SIG_1 [15:0], a 16 bit signal INPUT terminal U_RNG_dE8_15:0 ], a 16 bit signal INPUT terminal U_SIG_SIG_1-1 to U_ING_SIG_1 [15:0], and a 16 bit signal INPUT terminal U_SIG_SIG_1 [15:0] which are arranged in a column array, wherein the array represents that the number of the M_SIGN_1-N and the array represents the number of the N; the signals INPUT by the terminals U_ASSIGN, U_ SELEGT _ODD and U_SELECT_EVEN are used for controlling all the Ising node STATEs to be updated alternately, the Ising node coupling circuit calculates the energy change delta E of the two-dimensional Ising model based on the corresponding Ising node STATEs and the neighbor Ising node STATEs, controls the corresponding Ising node to overturn according to the Metropolis criterion according to the corresponding two-bit random bit values generated by the random bit stream generator, and completes simulation of the evolution process of the two-dimensional Ising model after multiple evolution, wherein the neighbor Ising node STATEs represent the upper, lower, left and right 4 neighbor Ising node STATEs. Further, the Ising node includes a first memristive cell, a second memristive cell, a first gate, a terminal RST, a terminal ASSIGN, a terminal SELECT, a terminal REVERSE, and a terminal STATE, the first memristor unit comprises a first threshold voltage type memristor, a first numerical control switch, a first current mirror, a first inverter, a second inverter, a first resistor, a second resistor, a first NMOS, the first PMOS and the second PMOS, the M1 end of the first threshold voltage type memristor is connected with a VDD power supply through the first resistor, the M1 end of the first threshold voltage type memristor is also connected with one end of the first numerical control switch and the drain electrode of the second PMOS respectively, the other end of the first numerical control switch is connected with the drain electrode of the first NMOS and the drain electrode of the first PMOS respectively, the source electrode of the first NMOS is connected with a VEE power supply, the source electrode of the first PMOS is connected with a VCC power supply, the s