CN-122021528-A - Functional unit creation method, related device, layout design method and storage medium

CN122021528ACN 122021528 ACN122021528 ACN 122021528ACN-122021528-A

Abstract

The application provides a functional unit creation method, a related device, a layout design method and a storage medium, which are applied to the technical field of computers, wherein the method firstly divides an integrated circuit into a plurality of logic areas based on a static time sequence analysis result and determines a target logic area, then extracts an initial circuit architecture in the target logic area, carries out architecture recombination on the initial circuit architecture to obtain a target circuit architecture with the same function as the initial circuit architecture, finally carries out physical design based on the target circuit architecture, the method is deep into the target logic area to conduct targeted optimization, and because the logic level of the target circuit architecture is smaller than that of the initial circuit architecture, the consumption of standard units in the target circuit architecture can be reduced, the time sequence performance of the logic area is improved, the time sequence performance of the slow logic area is improved, and the problem that the time sequence performance of the slow logic area in the related art limits the integral performance of the integrated circuit is solved.

Inventors

MA ZHUO
ZHANG XIAO
ZHANG WENHAN
Yue chaoyang
ZENG JIAXING

Assignees

飞腾信息技术有限公司

Dates

Publication Date: 20260512
Application Date: 20251230

Claims (13)

1. A functional unit creation method, comprising: Dividing the integrated circuit into a plurality of logic areas based on a static time sequence analysis result, and determining a target logic area in the plurality of logic areas; extracting an initial circuit architecture in the target logic area; Performing architecture reorganization on the initial circuit architecture to obtain a target circuit architecture, wherein the logic level number of the target circuit architecture is smaller than that of the initial circuit architecture and the logic level number is the same as that of the circuit of the initial circuit architecture; And performing physical design based on the target circuit architecture to obtain the functional unit corresponding to the target logic region.
2. The method of claim 1, wherein extracting the initial circuit architecture within the target logic region comprises: Detecting the data transmission process of each standard unit in the target logic area; if any standard unit in the target logic area can complete data transmission in a single clock period, extracting a circuit in the target logic area to obtain an initial circuit architecture.
3. The method of claim 1, wherein performing the architecture reorganization on the initial circuit architecture to obtain a target circuit architecture comprises: And carrying out logic function combination on the initial circuit architecture, and simplifying the circuit structure of the transistor level to obtain the target circuit architecture.
4. A method according to claim 3, wherein logically combining the initial circuit architecture comprises: And combining a plurality of standard units in the initial circuit architecture into a composite logic unit with equivalent logic function, wherein the standard units are mutually connected and are used for realizing the preset function of the initial circuit architecture.
5. A method according to claim 3, wherein transistor-level circuit structure simplification of the initial circuit architecture comprises: And combining the transistor circuits used for realizing the basic logic operation in the initial circuit architecture into a transistor circuit used for realizing the compound logic operation, wherein the basic logic operation comprises at least one of AND, OR and NOT, and the compound logic operation comprises at least one of OR and NAND, NOR and AND and NAND.
6. The method of claim 1, wherein physically designing based on the target circuit architecture to obtain the functional unit corresponding to the target logic area comprises: And performing layout, wiring and external port arrangement based on the target circuit architecture to obtain the layout of the functional unit corresponding to the target logic area.
7. The method of claim 6, wherein performing layout based on the target circuit architecture comprises: And arranging logic units in the time sequence paths adjacently according to the signal transmission direction of any time sequence path in the target circuit architecture so as to reduce the length of interconnection lines between the logic units, wherein the logic units comprise standard units and composite logic units obtained based on the combination of a plurality of standard units.
8. The method of claim 6, wherein routing based on the target circuit architecture comprises: And arranging the interconnection lines with the length larger than a preset length threshold value in the target circuit architecture and/or the interconnection lines in the target subareas in the target circuit architecture at a metal layer of a higher layer, wherein the target subareas are areas with the wiring density larger than a preset density threshold value in the target circuit architecture.
9. The method of claim 6, wherein the external port arrangement based on the target circuit architecture comprises: And arranging an external port of the target circuit architecture close to a logic unit connected with the external port, wherein the external port is not positioned at the boundary position of the functional unit.
10. A functional unit creation apparatus, characterized by comprising: A region dividing unit for dividing the integrated circuit into a plurality of logic regions based on the static timing analysis result, and determining a target logic region among the plurality of logic regions; An extracting unit, configured to extract an initial circuit architecture in the target logic area; The first optimizing unit is used for carrying out framework recombination on the initial circuit framework to obtain a target circuit framework, wherein the logic level number of the target circuit framework is smaller than that of the initial circuit framework and the logic level number is the same as the circuit function of the initial circuit framework; and the second optimizing unit is used for performing physical design based on the target circuit architecture to obtain the functional unit corresponding to the target logic area.
11. A layout design method, comprising: In response to a unit call instruction, a functional unit created according to the functional unit creation method as claimed in any one of claims 1 to 9 is called and added in the layout of the system on chip.
12. An electronic device comprising a memory, a processor and a computer program stored on the memory for execution by the processor, characterized in that the processor, when executing the computer program, implements the steps of the functional unit creation method according to any of claims 1 to 9 or the steps of the layout design method according to claim 11.
13. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the functional unit creation method according to any one of claims 1 to 9, or the steps of the layout design method according to claim 11.

Description

Functional unit creation method, related device, layout design method and storage medium Technical Field The application relates to the technical field of computers, in particular to a functional unit creation method, related equipment, a layout design method and a storage medium. Background In existing applications, designers use electronic design automation (Electronic Design Automation, EDA) tools to optimize integrated circuit designs, such as cell replacement methods, to replace small-drive standard cells with large-drive standard cells, or to perform wire-wrap optimization, to break long-delay interconnect lines, and then to increase the speed of the path by inserting buffers, etc. However, in the actual design process, the situation that the time sequence characteristics of part of logic areas have obvious differences often occurs, the functions of the logic areas are complex, a large number of standard units are used, and because the EDA tool is difficult to globally optimize all logic areas in the integrated circuit, the time sequence performance of each logic area is not balanced enough, the time sequence performance of each logic area at a low speed becomes a bottleneck which restricts the overall working frequency of the integrated circuit to be improved, and the overall performance of the integrated circuit is restricted to be further improved. Disclosure of Invention In view of this, the present application aims to provide a functional unit creating method, related apparatus, layout design method and storage medium, so as to solve the problem that the overall performance of the integrated circuit is further improved due to the time sequence performance of the slow logic area, which is difficult to globally optimize all logic areas in the integrated circuit in the related art. In a first aspect, the present application provides a functional unit creation method, including: Dividing the integrated circuit into a plurality of logic areas based on a static time sequence analysis result, and determining a target logic area in the plurality of logic areas; extracting an initial circuit architecture in the target logic area; Performing architecture reorganization on the initial circuit architecture to obtain a target circuit architecture, wherein the logic level number of the target circuit architecture is smaller than that of the initial circuit architecture and the logic level number is the same as that of the circuit of the initial circuit architecture; And performing physical design based on the target circuit architecture to obtain the functional unit corresponding to the target logic region. In an alternative embodiment, extracting the initial circuit architecture within the target logic region includes: Detecting the data transmission process of each standard unit in the target logic area; if any standard unit in the target logic area can complete data transmission in a single clock period, extracting a circuit in the target logic area to obtain an initial circuit architecture. In an alternative embodiment, the method for performing the architecture reorganization on the initial circuit architecture to obtain a target circuit architecture includes: and carrying out logic function combination on the initial circuit architecture and/or simplifying the circuit structure of the transistor level to obtain the target circuit architecture. In an alternative embodiment, the logic function combination of the initial circuit architecture includes: And combining a plurality of standard units in the initial circuit architecture into a composite logic unit with equivalent logic function, wherein the standard units are mutually connected and are used for realizing the preset function of the initial circuit architecture. In an alternative embodiment, the transistor-level circuit structure simplification of the initial circuit architecture includes: And combining the transistor circuits used for realizing the basic logic operation in the initial circuit architecture into a transistor circuit used for realizing the compound logic operation, wherein the basic logic operation comprises at least one of AND, OR and NOT, and the compound logic operation comprises at least one of OR and NAND, NOR and AND and NAND. In an optional implementation manner, performing physical design based on the target circuit architecture to obtain a functional unit corresponding to the target logic area, where the functional unit includes: And performing layout, wiring and external port arrangement based on the target circuit architecture to obtain the layout of the functional unit corresponding to the target logic area. In an alternative embodiment, performing layout based on the target circuit architecture includes: And arranging logic units in the time sequence paths adjacently according to the signal transmission direction of any time sequence path in the target circuit architecture so as to reduce the length of interconnection lin