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CN-122021529-A - Integrated circuit layout design method and device

CN122021529ACN 122021529 ACN122021529 ACN 122021529ACN-122021529-A

Abstract

The invention provides an integrated circuit layout design method and device. The method comprises the steps of preparing new design rules according to layer information of two-dimensional layout files and three-dimensional layout files in a three-dimensional integrated circuit and layout interconnection relations between the three-dimensional layout files and the two-dimensional layout files, carrying out layer mapping and layout merging on the two-dimensional layout files and the three-dimensional layout files to obtain new layout files, and adopting the new design rules to check and modify the new layout files until the new layout files pass the check. The invention can simplify the layout design and verification process and shorten the design period.

Inventors

  • HUANG SIYUAN

Assignees

  • 成都海光微电子技术有限公司

Dates

Publication Date
20260512
Application Date
20260123

Claims (10)

  1. 1. An integrated circuit layout design method, the method comprising: according to the layer information of each two-dimensional layout file and each three-dimensional layout file in the three-dimensional integrated circuit and the layout interconnection relationship between the three-dimensional layout files and each two-dimensional layout file, a new design rule is formulated; performing layer mapping and layout merging on the two-dimensional layout files and the three-dimensional layout files to obtain new layout files; And checking and modifying the new layout file by adopting the new design rule until the new layout file passes the checking.
  2. 2. The method according to claim 1, wherein the preparing a new design rule according to the layer information of each two-dimensional layout file and each three-dimensional layout file in the three-dimensional integrated circuit and the layout interconnection relationship between the three-dimensional layout file and each two-dimensional layout file comprises: respectively formulating corresponding new layer design rules for each new layer generated after layer mapping, wherein the new layer design rules are modified only by layer numbers compared with the design rules of the original layers corresponding to the new layers; according to the layout interconnection relation between the three-dimensional layout file and each two-dimensional layout file, establishing an interconnection design rule for checking the mutual influence between the three-dimensional layout file and each two-dimensional layout file; The original design rules corresponding to the two-dimensional layout files and the three-dimensional layout files, the new layer design rules and the interconnection design rules form the new design rules.
  3. 3. The method of claim 1, wherein performing layer mapping and layout merging on the two-dimensional layout file and the three-dimensional layout file to obtain a new layout file comprises: Carrying out layer number adjustment on layers with the same layer number in each two-dimensional layout file and each three-dimensional layout file so that the layer numbers of all the adjusted layers are different; And merging the two-dimensional layout files and the three-dimensional layout files subjected to layer number adjustment to obtain new layout files.
  4. 4. A method according to claim 2 or 3, wherein said checking said new layout file using said new design rules comprises: Checking each two-dimensional layout file and each three-dimensional layout file respectively by adopting original design rules corresponding to each two-dimensional layout file and each three-dimensional layout file; Checking a new layer generated after mapping the layer by adopting the new layer design rule; And checking the interaction between the three-dimensional layout file and each two-dimensional layout file by adopting the interconnection design rule.
  5. 5. The method according to claim 1, wherein the method further comprises: Splitting the new layout file passing the inspection so as to correspondingly deliver each two-dimensional layout file and each three-dimensional layout file which are obtained through splitting.
  6. 6. An integrated circuit layout design apparatus, the apparatus comprising: The design rule making unit is used for making a new design rule according to the layer information of each two-dimensional layout file and each three-dimensional layout file in the three-dimensional integrated circuit and the layout interconnection relationship between the three-dimensional layout file and each two-dimensional layout file; The layer mapping and layout merging unit is used for carrying out layer mapping and layout merging on the two-dimensional layout files and the three-dimensional layout files to obtain new layout files; and the checking unit is used for checking and modifying the new layout file by adopting the new design rule until the new layout file passes the check.
  7. 7. The apparatus of claim 6, wherein the design rule formulation unit comprises: The first formulating module is used for respectively formulating corresponding new layer design rules for each new layer generated after the mapping of the layers, wherein, the new layer design rules are modified only by the layer numbers compared with the design rules of the original layers corresponding to the new layers; The second formulating module is used for formulating an interconnection design rule for checking the mutual influence between the three-dimensional layout file and each two-dimensional layout file according to the layout interconnection relation between the three-dimensional layout file and each two-dimensional layout file; The original design rules corresponding to the two-dimensional layout files and the three-dimensional layout files, the new layer design rules and the interconnection design rules form the new design rules.
  8. 8. The apparatus according to claim 6, wherein the layer mapping and layout merging unit comprises: The layer mapping module is used for adjusting the layer numbers of the layers with the same layer numbers in each two-dimensional layout file and each three-dimensional layout file so that the layer numbers of the adjusted layers are different; The layout merging module is used for merging the two-dimensional layout files and the three-dimensional layout files subjected to layer number adjustment to obtain new layout files.
  9. 9. The apparatus according to claim 7 or 8, wherein the inspection unit comprises: The first checking module is used for checking each two-dimensional layout file and each three-dimensional layout file respectively by adopting original design rules corresponding to each two-dimensional layout file and each three-dimensional layout file; the second checking module is used for checking the new layer generated after the layer mapping by adopting the new layer design rule; and the third checking module is used for checking the interaction between the three-dimensional layout file and each two-dimensional layout file by adopting the interconnection design rule.
  10. 10. The apparatus of claim 6, wherein the apparatus further comprises: the layout splitting unit is used for splitting the new layout file passing the inspection so as to correspondingly deliver each two-dimensional layout file and each three-dimensional layout file which are obtained through splitting.

Description

Integrated circuit layout design method and device Technical Field The present invention relates to the field of integrated circuit design technology, and in particular, to a method and an apparatus for designing an integrated circuit layout. Background In integrated circuit design, the principle circuit design needs to rely on reasonable layout to realize the functions. The manufacturing capability and the substitution of different Fab (wafer factory) are different, and each Fab can formulate a special ref_rule (rule file for checking and matching the process node) for its own process node and provide the special ref_rule to the design end, so as to strictly limit the scheme of the design end to meet its own process manufacturing capability. If layer information that does not exist under the process node appears in the inspected layout design file, then these special layers will not be inspected by ref_rule. With the rapid development of advanced process, three-dimensional integrated circuits mainly characterized by vertical electrical connection are becoming a new development direction due to the advantages of high density and small size. Under advanced process nodes, bonding between several wafers (wafer) is typically involved, and a Bonding interface connects TSVs (Through Silicon Via, through silicon vias) through HB (Hybrid Bonding) structures for electrical transmission. Several wafers for bonding may come from different Fab process nodes, so the design end needs to consider the following issues at the same time when designing the cross-process node, taking as an example the process of bonding by 3d_fab_c and finally making 3d_die_c by 2d_die_a and 2d_die_b of two different 2d_fab process nodes: whether the 2d_die_a internal design meets the rule rule_a of 2d_fab_a; whether the 2d_die_b internal design meets the rule rule_b of 2d_fab_b; whether the 3D_die_C internal design meets the rule_C of the checking rule of 3D_Fab_C or not; Whether the key layers A1, A2 in 2d_die_a and the key layers B1, B2 in 2d_die_b meet the rule rule_c of 3d_fab_c, wherein A1, A2, B1, B2 are 2D layers strongly related to the 3D process. In the layout design of the cross-process node, by means of the inspection rules provided by each Fab, the layer information contained in die corresponding to the process node can be accurately inspected, but the key layers on two sides of the bonding interface are simultaneously present in the two process nodes, and the original inspection rules do not contain rule information of the key layers. In this case, in order to ensure the safety of the process flow, the design end needs to communicate 2d_fab and 3d_fab, and the inspection rule is customized for the key hierarchy so that both process nodes can inspect the same. Specifically, the design end firstly completes design and iteration on 2d_die_a and 2d_die_b separately according to rule_a and rule_b, then extracts key layers A1, A2, B1 and B2 of the two separately, combines with the process flow in 3d_fab_c, customizes 3d_die_c representing the 3D process separately, and combines with rule_c to modify and iterate, and meanwhile, the inspection content of rule_c also needs to be modified continuously along with the introduction of the key layers. In this process, each modification of 3d_die_c may cause a change in the key layers A1, A2, B1, B2, thereby causing further iterations of 2d_die_a and 2d_die_b, after multiple modifications and iterative updates, to finally fix 2d_die_a and 2d_die_b for delivery to 2d_fab, and 3d_die_c for delivery to 3d_fab. According to the design scheme, the key layers can be extracted to be connected with the 3D process layers in series after the 2D_die verification is correct, if the 3D_die verification fails, the 3D process layers can be modified by itself if errors only occur in the 3D process related layers, and if errors occur in the 2D key layers, the 2D_die must be returned to be redesigned and iterated, and the inspection is repeated. The whole process iteration link from 2D to 3D is too long and complex and is time-consuming, so that the layout design and verification process is long, and the design period is prolonged. Disclosure of Invention The integrated circuit layout design method and the integrated circuit layout design device provided by the invention can simplify the layout design and verification process and shorten the design period. In a first aspect, the present invention provides a method for designing an integrated circuit layout, including: according to the layer information of each two-dimensional layout file and each three-dimensional layout file in the three-dimensional integrated circuit and the layout interconnection relationship between the three-dimensional layout files and each two-dimensional layout file, a new design rule is formulated; performing layer mapping and layout merging on the two-dimensional layout files and the three-dimensional layout files to obtain new layout