CN-122021535-A - Circuit layout method, apparatus, computer device, storage medium, and program product

CN122021535ACN 122021535 ACN122021535 ACN 122021535ACN-122021535-A

Abstract

The invention relates to a circuit layout method, a circuit layout device, a computer device, a storage medium and a program product. The circuit layout method comprises the steps of combining circuit units meeting preset connection rules of the same type in a circuit topology structure diagram based on a signal flow algorithm to form unit groups, determining different array arrangement forms of the circuit units of each unit group to obtain a plurality of local layout schemes, wherein each array arrangement form forms one local layout scheme, arranging and combining the different local layout schemes corresponding to the unit groups to obtain a plurality of global layout schemes to be selected, and determining a target global layout scheme based on the global layout schemes to be selected. The full-flow automation of layout design is realized, the layout efficiency is remarkably improved, and the layout result is more in line with the design intent.

Inventors

LUO LIN
LI YANG
SU HONGCHANG
HE ZHONGJUN
LIU GUANGHUI
YANG LIU
SHAO YALI

Assignees

北京华大九天科技股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260303

Claims (10)

1. A circuit layout method, the circuit layout method comprising: based on a signal flow algorithm, circuit units meeting the same type of preset connection rules in a circuit topology structure diagram are combined to form a unit group; determining different array arrangement forms of circuit units of each unit group to obtain a plurality of local layout schemes, wherein each array arrangement form forms one local layout scheme; The different local layout schemes corresponding to the plurality of cell groups are arranged and combined to obtain a plurality of global layout schemes to be selected; And determining a target global layout scheme based on a plurality of the global layout schemes to be selected.
2. The circuit layout method according to claim 1, wherein the type of the preset connection rule includes any one of the following: The input end and the output end are connected by only one wire net; The signal source is provided with only one input end and is connected with the input end; marked as belonging to the same multi-bit device; the output end of a first circuit unit in the plurality of circuit units is connected with the input end of a second circuit unit in the plurality of circuit units, and the input end of the first circuit unit is connected with the output end of the second circuit unit to form the same feedback loop.
3. The circuit layout method according to claim 1, wherein after the circuit units satisfying the same type of preset connection rule in the circuit topology structure diagram are combined to form a unit group, the circuit layout method further comprises: When the number of the unit groups is greater than a preset number threshold, performing the following process until the number of the unit groups is less than or equal to the preset number threshold: selecting two unit groups to be combined from all the unit groups according to a preset judging rule; and combining the two unit groups to be combined into one unit group.
4. The circuit layout method according to claim 3, wherein the preset determination rule includes: The number of the circuit units included in the two unit groups to be combined is the same, and the types of the circuit units included in the two unit groups to be combined are completely the same; In all the cell groups, the combined outline area of the two cells to be combined is the smallest, and the number of identical nets inside the two cell groups to be combined is the largest.
5. The circuit layout method according to claim 1, wherein the determining a target global layout scheme based on a plurality of the candidate global layout schemes comprises: Scoring each global layout scheme to be selected according to an evaluation function, wherein the evaluation indexes of the evaluation function comprise area, line length, area utilization rate and overall symmetry; And selecting the global layout scheme to be selected with the highest score as the target global layout scheme.
6. The circuit layout method according to claim 5, wherein scoring each of the candidate global layout schemes according to an evaluation function comprises: For each evaluation index, carrying out normalization processing on the values of all the global layout schemes to be selected under the evaluation index to obtain normalized scores; and calculating the score of the global layout scheme to be selected according to the normalized score corresponding to each evaluation index and the corresponding weight coefficient.
7. A circuit arrangement device, the circuit arrangement device comprising: The merging module is configured to merge the circuit units meeting the same type of preset connection rules in the circuit topology structure diagram to form a unit group; the local layout module is configured to determine different array arrangement forms of the circuit units of each unit group, and a plurality of local layout schemes are obtained; The global layout module is configured to arrange and combine different local layout schemes corresponding to the plurality of cell groups to obtain a plurality of global layout schemes to be selected, and each array arrangement form forms one local layout scheme; and the selection module is configured to determine a target global layout scheme based on a plurality of the global layout schemes to be selected.
8. A computer device, the computer device comprising: A processor; a memory for storing the processor-executable instructions; wherein the processor is configured to perform the circuit layout method of any of claims 1 to 6.
9. A non-transitory computer readable storage medium, characterized in that instructions in the storage medium, when executed by a processor of a terminal, enable the terminal to perform the circuit layout method of any one of claims 1 to 6.
10. A computer program product comprising a computer program or instructions which, when executed by a processor, implements the circuit layout method of any of claims 1 to 6.

Description

Circuit layout method, apparatus, computer device, storage medium, and program product Technical Field The present invention relates to the field of circuit design, and in particular, to a circuit layout method, apparatus, computer device, storage medium, and program product. Background In integrated circuit design, layout design is a key element for converting circuit units in a circuit schematic into actual geometric positions. The layout design in the related art often depends on manpower, however, with the continuous reduction of the process nodes of the integrated circuit, the circuit scale is huge, if the layout is designed by manpower, a great deal of time is consumed, and the effect often hardly reaches the design expectation. Disclosure of Invention To overcome the problems in the related art, the present invention provides a circuit layout method, apparatus, computer device, storage medium, and program product. According to a first aspect of an embodiment of the present invention, there is provided a circuit layout method including: based on a signal flow algorithm, circuit units meeting the same type of preset connection rules in a circuit topology structure diagram are combined to form a unit group; determining different array arrangement forms of circuit units of each unit group to obtain a plurality of local layout schemes, wherein each array arrangement form forms one local layout scheme; The different local layout schemes corresponding to the plurality of cell groups are arranged and combined to obtain a plurality of global layout schemes to be selected; And determining a target global layout scheme based on a plurality of the global layout schemes to be selected. In some exemplary embodiments, the type of the preset connection rule includes any one of the following: The input end and the output end are connected by only one wire net; The signal source is provided with only one input end and is connected with the input end; marked as belonging to the same multi-bit device; the output end of a first circuit unit in the plurality of circuit units is connected with the input end of a second circuit unit in the plurality of circuit units, and the input end of the first circuit unit is connected with the output end of the second circuit unit to form the same feedback loop. In some exemplary embodiments, after the circuit units meeting the same type of preset connection rule in the circuit topology structure diagram are combined to form the unit group, the circuit layout method further includes: When the number of the unit groups is greater than a preset number threshold, performing the following process until the number of the unit groups is less than or equal to the preset number threshold: selecting two unit groups to be combined from all the unit groups according to a preset judging rule; and combining the two unit groups to be combined into one unit group. In some exemplary embodiments, the preset decision rule includes: The number of the circuit units included in the two unit groups to be combined is the same, and the types of the circuit units included in the two unit groups to be combined are completely the same; In all the cell groups, the combined outline area of the two cells to be combined is the smallest, and the number of identical nets inside the two cell groups to be combined is the largest. In some exemplary embodiments, the determining a target global layout scheme based on a plurality of the candidate global layout schemes includes: Scoring each global layout scheme to be selected according to an evaluation function, wherein the evaluation indexes of the evaluation function comprise area, line length, area utilization rate and overall symmetry; And selecting the global layout scheme to be selected with the highest score as the target global layout scheme. In some exemplary embodiments, said scoring each of said candidate global layout schemes according to an evaluation function comprises: For each evaluation index, carrying out normalization processing on the values of all the global layout schemes to be selected under the evaluation index to obtain normalized scores; and calculating the score of the global layout scheme to be selected according to the normalized score corresponding to each evaluation index and the corresponding weight coefficient. According to a second aspect of the embodiments of the present invention, there is provided a circuit layout apparatus comprising: The merging module is configured to merge the circuit units meeting the same type of preset connection rules in the circuit topology structure diagram to form a unit group; the local layout module is configured to determine different array arrangement forms of the circuit units of each unit group, and a plurality of local layout schemes are obtained; The global layout module is configured to arrange and combine different local layout schemes corresponding to the plurality of cell groups to obtain a plurali