CN-122021536-A - AI-assisted chip layout planning method and system

CN122021536ACN 122021536 ACN122021536 ACN 122021536ACN-122021536-A

Abstract

The invention discloses an AI-assisted chip layout planning method and system, and belongs to the technical field of integrated circuit physical design. The method comprises the steps of analyzing RTL codes to construct a directed weighted graph, adopting a graph neural network to learn module importance evaluation rules from the graph, combining area constraint to generate recommended area occupation ratio, analyzing a memory structure to generate memory placement suggestions matched with the direction of data flow, and synthesizing the information to generate module-level layout placement suggestions. According to the invention, the data flow interaction relation is automatically analyzed through the AI algorithm, so that manual intervention is reduced, the area allocation and the memory layout are optimized, the physical design iteration is accelerated, and the timing sequence convergence efficiency is improved.

Inventors

ZHENG SONGHAO
HUANG WEN
Ren qingyuan

Assignees

睿思芯科(深圳)技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260410

Claims (10)

1. An AI-assisted chip layout planning method, comprising the steps of: s1, analyzing RTL codes of a target chip, extracting signal connection relations and data read-write behaviors among modules and inside the modules, and constructing a directed weighted graph for representing data flow directions and fan-out characteristics; s2, learning module importance evaluation rules from the directed weighted graph by adopting a learning method based on a graph neural network, and generating recommended area occupation ratios of all modules by combining target area constraint of a chip or a subsystem and module placement boundary conditions; s3, analyzing a memory structure in the module, partitioning a memory according to a data access relation, and generating a memory placement suggestion matched with a data flow direction; And S4, integrating the recommended area ratio, the memory placement suggestions and the data flow interaction relationship among the modules to generate module-level layout placement suggestions.
2. The AI-assisted chip layout planning method of claim 1, wherein in step S1, the nodes of the directed weighted graph represent bottom layer functional modules, sub-modules or memory banks, the node attributes include module types, port numbers and minimum functional areas, the directed edges represent data driving or read-write interaction relations among the modules, and the edge weights are calculated according to the number of signal connections, the data read-write frequency and whether the key time sequence paths are present.
3. The AI-assisted chip layout planning method of claim 2, wherein the calculation formula of the edge weights is: ; Wherein the method comprises the steps of Is a module To the point of Is a number of signal connections; Is a module For a pair of Data read-write frequency of (2); The key path is identified; , , Is a configurable superparameter.
4. The AI-aided chip layout planning method of claim 1, wherein in step S2, said module importance evaluation rule includes computation of interaction density and timing criticality, said interaction density D i is computed by a module The sum of the weights of all the incoming edges and the outgoing edges divided by the sum of the weights of all the edges of the whole graph, the time sequence criticality Is composed of a module The critical path is the path with the smallest timing margin and the module is important Wherein Is a balance coefficient.
5. The AI-assisted chip layout planning method of claim 4 in which the recommended area ratio The calculation mode of (a) is as follows: ; wherein the basis area is a ratio of As determined by the minimum functional area of the device, As a basis weight of the area of the base, Is a module Is of importance in terms of (a) the importance of (c), Is a module And satisfies the total area constraint and the preset area upper and lower limit constraint.
6. The AI-assisted chip layout planning method according to claim 1, wherein steps S1 to S4 are implemented by a hybrid framework of a learning type method based on a graph neural network and an optimization type method based on heuristic search, wherein the learning type method is used for learning a mapping relation among module importance, interaction density and area distribution from the directed weighted graph, and the optimization type method is used for optimizing a module area allocation and layout scheme under an area constraint.
7. The AI-assisted chip layout planning method of claim 6 wherein training data of the learning-based method is derived from RTL, netlist, layout plan and timing congestion report of historical design project, and wherein a supervision tag includes congestion hotspot number, critical path timing margin and module level area utilization, the supervision tag is used to train the learning-based method.
8. The AI-assisted chip layout planning method of claim 1, wherein in step S4, the generated module-level layout placement proposal includes at least one of the following forms: the structured configuration file comprises module names, hierarchical attribution, placement coordinates, size and attribution area division information; a visual layout sketch is used for displaying the position distribution and interaction density of the modules in a graphical mode; The tool may execute a script for automatically completing the module level layout constraint settings in the physical design tool.
9. AI-assisted chip layout planning system for performing the AI-assisted chip layout planning method of any of claims 1-8, comprising: The RTL analysis module is used for analyzing RTL codes of the target chip, extracting signal connection relations and data read-write behaviors among the modules and in the modules, and constructing a directed weighted graph, wherein nodes of the directed weighted graph represent bottom layer functional modules, sub-modules or memory banks, node attributes comprise module types, port numbers and minimum functional areas, and directed edges represent data driving or read-write interaction relations among the modules; The area analysis module is used for learning module importance evaluation rules from the directed weighted graph by adopting a learning method based on a graph neural network, and generating recommended area occupation ratios of all modules by combining target area constraint of a chip or a subsystem and module placement boundary conditions; the memory layout module is used for analyzing the memory structure in the module and generating memory placement suggestions according to the data access relationship; The layout generation module is used for synthesizing the recommended area occupation ratio, the memory placement suggestions and the data flow interaction relationship among the modules to generate module-level layout placement suggestions.
10. The AI-assisted chip layout planning system of claim 9, wherein the module-level layout placement suggestion output by the layout generation module includes at least one of a structured configuration file, a visual layout sketch, and a tool-executable script.

Description

AI-assisted chip layout planning method and system Technical Field The invention relates to the technical field of integrated circuit physical design, in particular to an AI-assisted chip layout planning method and system, which are suitable for comprehensive optimization of module layout, data flow direction, fan-out relation, area allocation and storage unit placement in high-performance processors and complex system-on-chip (SoC) design. Background In the physical design process of modern high-performance processors and large-scale SoCs, the rationality of layout planning (Floorplan) directly affects the congestion condition, timing performance and power consumption performance of subsequent layout and wiring. An unreasonable layout plan often results in subsequent rounds of iterative adjustment, significantly lengthening the design cycle. The existing layout planning and design process generally relies on detailed analysis of Register Transfer Level (RTL) codes by engineers and requires a great deal of communication with micro-architecture designers to confirm the data transfer direction between modules, interface relationships, placement locations of ports (pins), and organization of logic and memory cells within the modules. On this basis, engineers initially place each functional module and the memory (memory) inside the module according to personal experience. However, the method has the following defects that firstly, the rationality of layout planning is usually developed after multiple rounds of layout wiring and time sequence analysis, the number of design iterations is large, the time sequence and performance convergence speed is low, secondly, the layout planning design process is highly dependent on the communication efficiency among designers, once information is not timely or fully transferred, unreasonable placement decisions are easily introduced, and furthermore, the process is seriously dependent on the personal experience and team cooperation capability of engineers, the consistency of design results among different personnel is poor, and the overall design quality is difficult to guarantee stably. Disclosure of Invention The invention aims to provide an AI-assisted chip layout planning method and system, which automatically analyze the data flow direction, logic interaction relation, inter-module fan-out condition and port connection characteristics in RTL codes through an algorithm, and automatically generate reasonable layout planning and placing suggestions under the condition of reducing manual participation as much as possible, thereby accelerating the iterative process of physical design and improving the convergence efficiency of time sequence and performance. In order to achieve the above object, the present invention provides an AI-assisted chip layout planning method, comprising the steps of: And S1, analyzing RTL codes of the target chip, extracting signal connection relations and data read-write behaviors among modules and inside the modules, and constructing a directed weighted graph for representing the direction of a data stream and fan-out characteristics. Through the step, the interactive relation among the modules can be automatically extracted from the RTL codes to form the structured data which can be processed by the algorithm. And S2, learning a module importance evaluation rule from the directed weighted graph by adopting a learning method based on a Graph Neural Network (GNN), and generating a recommended area occupation ratio of each module by combining target area constraint of a chip or a subsystem and module placement boundary conditions. The module placement boundary conditions comprise physical constraints such as the overall shape of a chip or a subsystem, core area limitation, power ring positions, input/output port distribution and the like, and are used for limiting a feasible area of module placement, so that a placement scheme is ensured to accord with the overall physical design specification of the chip. According to the method, the high-dimensional interaction characteristics among the GNN capturing modules are utilized, the influence weight of the learning module on the time sequence and the congestion is utilized, the area distribution is carried out based on objective data driving, unreasonable distribution caused by experience differences of engineers is avoided, and the congestion and the time sequence risk are reduced from the source. And S3, analyzing a memory structure in the module, partitioning a memory according to the data access relation, and generating a memory placement suggestion matched with the data flow direction. The step aligns the division of the memory bank with the data flow direction, reduces the data access delay and the wiring complexity of the cross-region, and improves the memory access efficiency. And S4, integrating the recommended area ratio, the memory placement suggestions and the data flow interaction relationsh