CN-122021540-A - Layout wiring method and device for chip power switch and readable storage medium

CN122021540ACN 122021540 ACN122021540 ACN 122021540ACN-122021540-A

Abstract

The application discloses a layout wiring method and device of a chip power switch and a readable storage medium, and relates to the technical field of integrated circuit design. The method comprises the steps of determining a power-down area where the voltage drop of a power switch on a target chip does not meet the preset voltage drop requirement in the process of signing the target chip, wherein the target chip comprises a plurality of initial power switches and initial power supply wirings which are inserted in a layout wiring stage, inserting newly-increased power switches into a target area on the target chip locally based on the number of the initial power switches contained in the power-down area, and adjusting the initial power supply wirings corresponding to the target area into power supply wirings for the newly-increased power switches.

Inventors

MIAO QIANQIAN
LIU MINJIE
MENG TIANXIANG
YAN QIANG
CHEN XUAN

Assignees

联芸科技(杭州)股份有限公司

Dates

Publication Date: 20260512
Application Date: 20260211

Claims (10)

1. The layout wiring method of the chip power switch is characterized by comprising the following steps of: In the process of signing a target chip, determining a power-down area in which the voltage drop of a power switch on the target chip does not meet the preset voltage drop requirement, wherein the target chip comprises a plurality of initial power switches and initial power supply wirings which are inserted in a layout wiring stage; Based on the number of the initial power switches contained in the power-down area, locally inserting a newly-added power switch into a target area on the target chip; And adjusting the initial power supply wiring corresponding to the target area to be the power supply wiring for the newly added power switch.
2. The method of claim 1, wherein the locally inserting a new power switch in the target area on the target chip based on the number of initial power switches included in the power down area comprises: if the number of the initial power switches inserted in the columns contained in the power-down area is not 0 and is smaller than the preset number, adding an actual power supply with a preset length along the columns in a target blank area around the power-down area on the target chip; inserting a corresponding number of newly-added power switches with preset lengths below the actual power supply; Moving the number of newly-added power switches to a target position in the power-down area; and determining the target area based on the target position and locally inserting the newly-added power switch.
3. The method of claim 2, wherein moving the number of newly added power switches to a target location within the power down region comprises: the number of the newly added power switches are moved and inserted into the corresponding positions of the longitudinal interval areas between every two initial power switches in the power-down area in a longitudinal interval mode, or Moving the initial power switch in the power-down region to the corresponding position of the first region in the power-down region in a longitudinal interval manner, moving the number of the newly added power switches to the corresponding position of the second region in the power-down region in a longitudinal interval manner, wherein the first region and the second region are longitudinally spaced, or And moving a first number of the newly-increased power switches in the number to the corresponding position of a longitudinal interval region between every two initial power switches in the power-down region in a longitudinal interval manner, moving the initial power switches in the power-down region to the corresponding position of a first region in the power-down region in the longitudinal interval manner, and moving a second number of the newly-increased power switches except the first number in the number to the corresponding position of a second region in the power-down region in the longitudinal interval manner, wherein the first region and the second region are longitudinally spaced.
4. The method of claim 2, further comprising, after moving the number of newly added power switches to a target location within the power down region: And deleting the actual power supply added by the target blank area.
5. A method according to claim 3, wherein adjusting the initial supply wiring corresponding to the target area to the supply wiring for the newly added power switch comprises: If the locally inserted newly-added power switch is provided with a grounding end and the lowest metal layer of the initial power supply wiring of the target chip is transversely penetrated, cutting and deleting the ground wire of the lowest metal layer of the target area based on the positions of the number of the newly-added power switches; and adding a power supply wiring for the newly added power switch in the target area.
6. The method of claim 1, wherein the locally inserting a new power switch on the target chip based on the number of initial power switches contained in the power down region comprises: If the number of the initial power switches inserted in the row in the power-down area is 0, adding an actual power supply with a preset length along the row in a target blank area around the power-down area on the target chip, wherein the preset length is the same as the power-down area; inserting a corresponding number of newly-added power switches with preset lengths below the actual power supply; And determining the target area based on the insertion positions of the number of the newly added power switches and locally inserting the newly added power switches.
7. The method of claim 6, wherein adjusting the initial power supply wiring corresponding to the target area to the power supply wiring for the newly added power switch comprises: deleting initial power supply wiring corresponding to the target area based on the positions of the number of newly added power switches; and adding a power supply wiring for the newly added power switch in the target area.
8. The method according to any one of claims 2 to 7, wherein inserting a corresponding number of newly added power switches of the preset length below the actual power supply comprises: determining the insertion area based on the size and the position of the actual power supply and the width of the newly added power switch; and inserting a corresponding number of newly-increased power switches into the insertion area based on a preset power switch interval and the preset length.
9. A chip power switch arrangement comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, performs the steps of the method as claimed in any one of claims 1 to 8.
10. A readable storage medium, characterized in that it has stored thereon a program or instructions which, when executed by a processor, implement the steps of the method according to any of claims 1-8.

Description

Layout wiring method and device for chip power switch and readable storage medium Technical Field The present application relates to the field of integrated circuit design technologies, and in particular, to a method and apparatus for layout and routing of a chip power switch, and a readable storage medium. Background Power shutdown (APR) technology is a method commonly used in the field of low-power design of integrated circuits, and is usually implemented by inserting a power switch (power switch) in advance using an Auto Place and Route (APR) tool in a chip advanced place and Route stage. The number of power switches inserted directly affects the performance of the chip, and too small the number of the power switches inserted causes large dynamic power consumption (dynamic power) and voltage drop (IR drop), but too large the number of the power switches inserted causes resource waste, and the power switches themselves consume power consumption. Therefore, the planning of the number and arrangement of the power switches is a very important link in the early stage of layout and wiring. However, in actual engineering projects, although the early stage of layout and wiring is considered to provide the optimal power switch planning, in the later stage of chip signature (singnoff), the power switch inserted in the target area of the power switch or in the vicinity of the macro (macro) unit is often turned off too much, and the voltage drop (IR drop) causes the voltage drop of the power switch to not meet the preset voltage drop requirement. In order to ensure the working performance of the power switch, it is necessary to redesign the overall layout wiring of the chip, and to use the APR tool to re-route the wiring according to the new overall layout wiring. Thus, the large-scale re-layout leads to the lengthening of the chip design period, and the design flow takes a long time and affects the subsequent chip (tapeout) process. Disclosure of Invention The embodiment of the application aims to provide a layout wiring method and device of a chip power switch and a readable storage medium, which are used for solving the problem of long design time consumption caused by re-integrally updating the chip layout in the post-signing period. In order to solve the technical problems, the present specification is implemented as follows: In a first aspect, a method for laying out and wiring a chip power switch is provided, including: In the process of signing a target chip, determining a power-down area in which the voltage drop of a power switch on the target chip does not meet the preset voltage drop requirement, wherein the target chip comprises a plurality of initial power switches and initial power supply wirings which are inserted in a layout wiring stage; Based on the number of the initial power switches contained in the power-down area, locally inserting a newly-added power switch into a target area on the target chip; And adjusting the initial power supply wiring corresponding to the target area to be the power supply wiring for the newly added power switch. Optionally, based on the number of initial power switches included in the power-down area, locally inserting a new power switch in a target area on the target chip, including: if the number of the initial power switches inserted in the columns contained in the power-down area is not 0 and is smaller than the preset number, adding an actual power supply with a preset length along the columns in a target blank area around the power-down area on the target chip; inserting a corresponding number of newly-added power switches with preset lengths below the actual power supply; Moving the number of newly-added power switches to a target position in the power-down area; and determining the target area based on the target position and locally inserting a new power switch. Optionally, based on the number of initial power switches included in the power-down area, locally inserting a new power switch on the target chip, including: If the number of the initial power switches inserted in the row in the power-down area is 0, adding an actual power supply with a preset length along the row in a target blank area around the power-down area on the target chip, wherein the preset length is the same as the power-down area; inserting a corresponding number of newly-added power switches with preset lengths below the actual power supply; And determining the target area based on the insertion positions of the number of the newly added power switches and locally inserting the newly added power switches. Optionally, inserting a number of newly added power switches corresponding to the preset length below the actual power supply, including: determining the insertion area based on the size and the position of the actual power supply and the width of the newly added power switch; and inserting a corresponding number of newly-increased power switches into the insertion area based on a pres