CN-122021541-A - Data characterization processing method of functional unit, related equipment and storage medium

CN122021541ACN 122021541 ACN122021541 ACN 122021541ACN-122021541-A

Abstract

The application provides a data characterization processing method of a functional unit, a related device and a storage medium, which are applied to the technical field of computers, wherein the method is used for carrying out data characterization processing on a target functional unit, any time sequence arc of the target functional unit at most comprises a time sequence logic unit, after the target functional unit is acquired, each time sequence path in the target functional unit is subjected to time sequence arc merging operation, the target functional unit is subjected to simulation test based on the combined time sequence arcs to obtain the characteristic data of the target functional unit, and the time sequence arcs of the target functional unit are combined before the characteristic data are acquired, so that the number of circuit state combinations needing simulation in the simulation test process can be greatly reduced, the simulation test duration is further shortened, the efficiency of acquiring the characteristic data is improved, and the overall design efficiency of the integrated circuit is correspondingly improved.

Inventors

ZHANG XIAO
ZHANG WENHAN
MA ZHUO
Ke Menjun
SUN JINGYA
Ma Lixue

Assignees

飞腾信息技术有限公司

Dates

Publication Date: 20260512
Application Date: 20251230

Claims (13)

1. A method for characterizing data of a functional unit, comprising: acquiring a target functional unit, wherein the target functional unit is used for realizing a preset function of an integrated circuit, and any time sequence arc in the target functional unit at most comprises a time sequence logic unit; performing time sequence arc merging operation on each time sequence path in the target functional unit; and performing simulation test on the target functional unit based on the combined time sequence arcs to obtain the characteristic data of the target functional unit.
2. The method of claim 1, wherein performing a timing arc merge operation for each timing path in the target functional unit comprises: Taking each time sequence path in the target functional unit as a target time sequence path in turn; Determining a target stage gate stage circuit in a multi-stage gate stage circuit included in the target timing path; Acquiring the time sequence delay time length from the time sequence path starting point to the target stage gate stage circuit of the target time sequence path; and merging the time sequence arcs of the target time sequence path before the target stage gate stage circuit according to the time sequence delay duration.
3. The method of claim 2, wherein obtaining the timing delay duration of the target timing path from a timing path start point to the target gate stage circuit comprises: Traversing all input value combinations of other timing paths than the target timing path; And aiming at each input value combination, acquiring the time sequence delay duration from the time sequence path starting point to the target stage gate-level circuit of the target time sequence path.
4. A method according to claim 3, wherein merging the timing arcs of the target timing path before the target stage gate stage circuit according to the timing delay duration comprises: determining a time sequence delay fluctuation time length according to a plurality of time sequence delay time lengths corresponding to the target time sequence path; If the time sequence delay fluctuation duration is within a preset duration range, merging the time sequence arc from the starting point of the time sequence path to the front of the target-stage gate-stage circuit into a time sequence arc; And if the time sequence delay fluctuation time length is not in the preset time length range, determining a target stage gate stage circuit in the multi-stage gate stage circuits included in the target time sequence path again until the time sequence arcs from the starting point of the time sequence path to the front of the target stage gate stage circuit are combined into one time sequence arc.
5. The method of claim 4, wherein determining a timing delay fluctuation duration from a plurality of timing delay durations corresponding to the target timing path comprises: determining a maximum time sequence delay duration and a minimum time sequence delay duration in a plurality of time sequence delay durations corresponding to the target time sequence path; And determining the difference between the maximum time sequence delay time length and the minimum time sequence delay time length as the time sequence delay fluctuation time length.
6. The method of claim 2, wherein determining a target stage gate stage circuit among the plurality of stage gate stage circuits included in the target timing path comprises: And sequentially taking each stage of gate circuits as target stage gate circuits along the direction facing the starting point of the time sequence path from the last stage of gate circuits in the multi-stage gate circuits included in the target time sequence path, wherein the last stage of gate circuits are gate circuits adjacent to the end point of the time sequence path in the multi-stage gate circuits.
7. The method of claim 2, wherein determining a target stage gate stage circuit among the plurality of stage gate stage circuits included in the target timing path comprises: And taking any one stage of the multi-stage gate stage circuits included in the target time sequence path as a target stage gate stage circuit.
8. The method according to any one of claims 2 to 7, wherein performing a simulation test on the target functional unit based on the combined timing arcs to obtain characterization data of the target functional unit includes: obtaining simulation excitation data and simulation process corner data; generating a plurality of simulation files based on the simulation excitation data and the simulation process corner data; respectively carrying out simulation test on the target functional units after the combination time sequence arcs according to each simulation file to obtain simulation test data; And determining the characteristic data of the target functional unit according to the simulation test data.
9. The method of claim 8, wherein the target gate level circuit includes at least one input, the simulation test data includes timing delay data, dynamic power consumption data, and leakage power consumption data, and the leakage power consumption data includes leakage power consumption of each output of the target functional unit; Determining characterization data of the target functional unit according to the simulation test data, including: acquiring time sequence delay duration and dynamic power consumption of each time sequence path in a pre-stage circuit connected with a target input end, wherein the target input end is any one of the at least one input end; determining time sequence characterization data and dynamic power consumption characterization data of the target functional unit based on time sequence delay duration and dynamic power consumption of each time sequence path in the front-stage circuit; And determining the average value of the leakage power consumption of each output end as the leakage power consumption characterization data of the target functional unit.
10. The method of claim 9, further comprising generating a standard library file for the target functional unit based on the timing characterization data, dynamic power consumption characterization data, and leakage power consumption characterization data.
11. A data characterization processing device of a functional unit, comprising: The device comprises an acquisition unit, a timing logic unit and a control unit, wherein the acquisition unit is used for acquiring a target functional unit, the target functional unit is used for realizing the preset function of an integrated circuit, and any timing arc in the target functional unit at most comprises the timing logic unit; The time sequence arc merging unit is used for carrying out time sequence arc merging operation on each time sequence path in the target functional unit; And the data processing unit is used for performing simulation test on the target functional unit based on the combined time sequence arcs to obtain the characteristic data of the target functional unit.
12. An electronic device comprising a memory, a processor and a computer program stored on the memory for execution by the processor, characterized in that the processor, when executing the computer program, implements the steps of the data characterization method of the functional unit of any of claims 1 to 10.
13. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the data characterization method of a functional unit according to any of claims 1 to 10.

Description

Data characterization processing method of functional unit, related equipment and storage medium Technical Field The present application relates to the field of computer technologies, and in particular, to a data characterization processing method for a functional unit, a related device, and a storage medium. Background In the field of integrated circuit design, a standard cell library is a basic stone for physical design, and each standard cell in the library needs to provide a set of complete characterization data, wherein the most critical is time sequence data and power consumption data, and the accuracy of the characterization data directly influences the final performance and yield of the integrated circuit after the integrated circuit is subjected to film streaming. Along with the continuous evolution of integrated circuit design to high performance and high energy efficiency, customized functional units with higher integration level and more complex logic functions are widely adopted in the design, and the application of the complex functional units in the design process necessarily needs the support of the characteristic data, however, the functional units usually have numerous input/output ports and internal circuit states, and the number of circuit state combinations needing simulation is exponentially increased in the process of extracting the characteristic data of the functional units in the related technology, so that the time consumption of the characteristic process is extremely long, the data volume is extremely huge, the characteristic data of the functional units are difficult to obtain efficiently, and the overall design efficiency of the integrated circuit is reduced. Disclosure of Invention In view of the foregoing, the present application is directed to a data characterization processing method for a functional unit, a related device, and a storage medium, so as to solve the problem that the extraction efficiency of the characterization data of the functional unit is low and the overall design process of the integrated circuit is affected in the related art. In a first aspect, the present application provides a data characterizing processing method of a functional unit, including: acquiring a target functional unit, wherein the target functional unit is used for realizing a preset function of an integrated circuit, and any time sequence arc in the target functional unit at most comprises a time sequence logic unit; performing time sequence arc merging operation on each time sequence path in the target functional unit; and performing simulation test on the target functional unit based on the combined time sequence arcs to obtain the characteristic data of the target functional unit. In an alternative embodiment, performing a timing arc merge operation on each timing path in the target functional unit includes: Taking each time sequence path in the target functional unit as a target time sequence path in turn; Determining a target stage gate stage circuit in a multi-stage gate stage circuit included in the target timing path; Acquiring the time sequence delay time length from the time sequence path starting point to the target stage gate stage circuit of the target time sequence path; and merging the time sequence arcs of the target time sequence path before the target stage gate stage circuit according to the time sequence delay duration. In an alternative embodiment, acquiring the time delay duration of the target time sequence path from the time sequence path starting point to the target gate level circuit includes: Traversing all input value combinations of other timing paths than the target timing path; And aiming at each input value combination, acquiring the time sequence delay duration from the time sequence path starting point to the target stage gate-level circuit of the target time sequence path. In an alternative embodiment, merging the timing arcs of the target timing path before the target stage gate stage circuit according to the timing delay duration includes: determining a time sequence delay fluctuation time length according to a plurality of time sequence delay time lengths corresponding to the target time sequence path; If the time sequence delay fluctuation duration is within a preset duration range, merging the time sequence arc from the starting point of the time sequence path to the front of the target-stage gate-stage circuit into a time sequence arc; And if the time sequence delay fluctuation time length is not in the preset time length range, determining a target stage gate stage circuit in the multi-stage gate stage circuits included in the target time sequence path again until the time sequence arcs from the starting point of the time sequence path to the front of the target stage gate stage circuit are combined into one time sequence arc. In an alternative embodiment, determining the timing delay fluctuation duration according to the plurality of timing de