CN-122021542-A - High-performance integrated circuit layout verification method and system

CN122021542ACN 122021542 ACN122021542 ACN 122021542ACN-122021542-A

Abstract

The invention relates to the technical field of integrated circuit design automation, in particular to a high-performance integrated circuit layout verification method which comprises the following steps of optimally encoding Manhattan directions, 45-degree edges and any angle edges by analyzing layout geometric characteristics, storing relative coordinate differences, dividing a layout into zones with balanced loads by using layout density analysis and machine learning prediction and combining data locality and cache optimization strategies, reducing memory access delay by combining a layered memory architecture and a prefetching mechanism, performing incremental updating and multi-condition query by combining Web real-time rendering and AI error classification, and obtaining an interactive verification report supporting collaborative evaluation. The invention solves the problems of low memory efficiency, insufficient computing efficiency, poor architecture expandability and low data representation.

Inventors

LIN YIZHOU
DU YU
LI QINGCHANG

Assignees

上海日观芯设技术有限公司

Dates

Publication Date: 20260512
Application Date: 20260122

Claims (10)

1. The high-performance integrated circuit layout verification method is characterized by comprising the following steps of: Optimizing and encoding the Manhattan direction, 45 degrees and any angle sides by analyzing the geometric characteristics of the layout, and storing the relative coordinate difference value to obtain layout data with high compression ratio; Dividing the layout into zones with balanced loads by using layout density analysis and machine learning prediction and combining data locality and cache optimization strategies to obtain optimized parallel computing units; the multi-thread dynamic task allocation is realized by combining a real-time monitoring system resource and task state with a work stealing algorithm and data affinity scheduling, so that a calculation resource allocation scheme with high efficiency is obtained; converting DRC rules into a graphical node structure, and applying a common sub-expression elimination and operation fusion strategy to obtain a rule execution dependency graph; Integrating SIMD instruction sets to accelerate geometric calculation, combining a layered memory architecture and a prefetching mechanism, reducing memory access delay, and obtaining a high-efficiency data processing flow with low memory occupation; And through incremental updating of an error database and multi-condition query, combining Web real-time rendering and AI error classification, obtaining an interactive verification report supporting collaborative review.
2. The method for verifying a layout of a high-performance integrated circuit according to claim 1, wherein the step of optimizing and encoding the manhattan direction, 45 degrees and any angle sides by analyzing the geometric characteristics of the layout, and storing the relative coordinate difference values to obtain layout data with high compression ratio comprises the following steps: By adopting a depth analysis method for geometric characteristics of the layout, extracting relative coordinate differences between adjacent vertexes to serve as a coding basis by identifying distribution rules of Manhattan direction edges, 45-degree direction edges and any angle edges; respectively adopting a direction bit and length bit combination code for a horizontal side, a vertical side and a 45-degree side, using an extension code mark for any angle side, and storing optimized relative coordinate data instead of absolute coordinates; And obtaining vertex data with the compression ratio of 4:1 and high-efficiency storage layout data with the overall layout compression ratio of 60% -70% through an encoding strategy.
3. The method for verifying a layout of a high-performance integrated circuit according to claim 1, wherein the layout is divided into zones with balanced loads by using layout density analysis and machine learning prediction and combining data locality and cache optimization strategies to obtain optimized parallel computing units, and the method comprises the following steps: Extracting geometric element distribution characteristics by traversing layout data by adopting a layout density analysis technology, and predicting Zone division size by combining a machine learning model; taking the geometric density of the layout, the computational complexity and the data access locality as division basis, and dynamically adjusting the Zone boundary by using cache line alignment optimization and a memory access mode prediction strategy; and ensuring the uniform distribution of the partition data quantity and the calculation intensity through a load balancing algorithm, dividing the layout into parallel calculation units with continuous memory access and balanced calculation load, and obtaining the optimized execution partition adapting to the hardware resource characteristics.
4. The method for verifying the layout of the high-performance integrated circuit according to claim 1, wherein the method for realizing multithread dynamic task allocation by monitoring system resources and task states in real time and combining a work stealing algorithm and data affinity scheduling to obtain a calculation resource allocation scheme with high efficiency comprises the following steps: A real-time monitoring mechanism is adopted, and the CPU core utilization rate, the memory bandwidth and the task queue length index are extracted through periodically collecting the system resource occupancy rate and the task execution state data; Combining a work stealing algorithm with a data affinity principle, and dynamically adjusting a task allocation strategy; When the idle thread is detected, the ready task is automatically migrated from the high-load thread to the idle thread, the data block of the migrated task is ensured to be positioned in the target thread cache hit range, and a dynamic load balancing distribution scheme is obtained through the scheduling strategy.
5. The method of verifying a layout of a high performance integrated circuit of claim 1, wherein converting DRC rules into a patterned node structure, applying a common sub-expression elimination and operation fusion strategy, obtaining rule execution dependency graphs, comprises the steps of: Extracting Boolean operation, geometric check and data dependency relationship thereof by analyzing semantic features of DRC rules by adopting a rule diagram structuring method; converting each rule into a standardized node structure comprising an input layer, an operation layer and an output layer, wherein the node type comprises an original layer, a Boolean operation layer and a derivative layer; And identifying a repeated calculation module by using a common sub-expression elimination technology, merging adjacent geometric operations by operating a fusion strategy, and generating a rule execution dependency graph with hierarchical data flow characteristics to obtain an optimized rule structure.
6. The method for verifying a layout of a high performance integrated circuit according to claim 1, wherein the integrated SIMD instruction set accelerates geometric computation, and reduces memory access delay by combining a hierarchical memory architecture and a prefetch mechanism, thereby obtaining a high-efficiency data processing flow with low memory occupation, comprising the steps of: Adopting a SIMD instruction set optimization technology, and extracting geometrical characteristics for parallel calculation by carrying out parallel processing on batch data in geometrical operation by vectorization calculation instructions, wherein the geometrical characteristics comprise vertex coordinates and side lengths; combining the layered memory architecture, storing the compressed layout data in a global shared memory, and caching the decompressed active data in a Zone cache pool; the data processed currently is kept in a thread local memory, geometric data of the next access area is prefetched through a machine learning prediction algorithm, asynchronous data loading is achieved, and an efficient data processing flow is obtained.
7. The method for verifying a layout of a high-performance integrated circuit according to claim 1, wherein the step of obtaining the interactive verification report supporting collaborative review by combining Web real-time rendering and AI error classification through incremental updating of an error database and multi-condition query comprises the following steps: Adopting an error database increment updating mechanism, extracting newly-added error information by recording the space-time index and version difference of the verification result, and synchronizing the newly-added error information with a multi-version result library; combining a multi-condition combined query engine, wherein the multi-condition combined query engine supports quick retrieval according to error types, region coordinates and process layers; and integrating a Web real-time rendering technology, carrying out interactive display on billions-level graphic data at a browser end through streaming, and carrying out intelligent classification labeling on geometric violations by using an AI error pattern recognition algorithm to obtain an interactive verification report which comprises a real-time collaborative review function and supports multi-user labeling.
8. A high performance integrated circuit layout verification system, the high performance integrated circuit layout verification system comprising: the layout data module is used for optimally encoding the Manhattan direction, 45-degree and any angle edges by analyzing the geometric characteristics of the layout, and storing the relative coordinate difference values to obtain layout data with high compression ratio; The parallel computing module is used for dividing the layout into zones with balanced loads by utilizing layout density analysis and machine learning prediction and combining data locality and a cache optimization strategy to obtain an optimized parallel computing unit; the resource allocation module is used for realizing multithread dynamic task allocation by combining a work stealing algorithm and data affinity scheduling through real-time monitoring of system resources and task states, so as to obtain a calculation resource allocation scheme with high efficiency; the rule conversion module is used for converting the DRC rule into a graphical node structure, and applying a common sub-expression elimination and operation fusion strategy to obtain a rule execution dependency graph; The data processing module is used for integrating the SIMD instruction set to accelerate geometric calculation, combining a layered memory architecture and a prefetching mechanism, reducing memory access delay and obtaining a high-efficiency data processing flow with low memory occupation; and the interactive verification module is used for obtaining an interactive verification report supporting collaborative review by combining Web real-time rendering and AI error classification through error database incremental updating and multi-condition query.
9. A high performance integrated circuit layout verification device comprising a memory and at least one processor, the memory having instructions stored therein, the at least one processor invoking the instructions in the memory to cause the high performance integrated circuit layout verification device to perform the steps of the high performance integrated circuit layout verification method of any of claims 1-7.
10. A computer readable storage medium having instructions stored thereon, which when executed by a processor, perform the steps of the high performance integrated circuit layout verification method of any of claims 1 to 7.

Description

High-performance integrated circuit layout verification method and system Technical Field The invention belongs to the technical field of integrated circuit design automation, and particularly relates to a high-performance integrated circuit layout verification method and system. Background In the context of the evolution of semiconductor technology nodes to 5nm and below, the complexity and data volume of integrated circuit layouts are characterized by exponential growth. Modern chip designs may contain hundreds of billions of transistors whose physical layout data size easily reaches the TB level. However, conventional Design Rule Checking (DRC) tools expose multiple technical defects in this environment, which becomes a critical bottleneck in the chip design cycle. First, memory inefficiency is one of the major problems faced by conventional DRC tools. These tools generally need to load the whole TB-level layout data into the memory, resulting in a drastic increase in the demand for memory resources, forming a memory bottleneck, and not being able to effectively adapt to the processing requirements of large-scale layout data under advanced process nodes. Second, the lack of computational efficiency severely constrains the performance of conventional DRC tools. The single-thread processing mode is difficult to cope with the physical verification requirement of a modern large-scale chip, so that the processing speed is slow, and the chip design verification period is remarkably prolonged. In addition, architecture scalability and data representation inefficiency are also issues to be addressed by conventional DRC tools. Limited by self-architecture design, the tools are difficult to flexibly support the updating of novel design rules and the expansion of new inspection requirements, and meanwhile, the layout data representation method has defects, so that a large amount of storage space is wasted, and the cost and efficiency of data processing and storage are further increased. Therefore, developing a high-performance and high-capacity integrated circuit layout verification method to solve the technical bottlenecks in the aspects of memory efficiency, computing efficiency, architecture expandability, data representation and the like becomes an urgent need in the current chip design field. The prior art has the defects of low memory efficiency, low calculation efficiency, poor architecture expandability and low data representation, and is difficult to cope with the processing requirement of TB-level layout data under process nodes of 5nm and below, so that the chip design verification period is long, the cost is high, and the development requirement of advanced integrated circuit design cannot be met. Disclosure of Invention Aiming at the current situation, the invention provides a high-performance integrated circuit layout verification method and a system, which can solve the problems of low memory efficiency, insufficient calculation efficiency, poor architecture expandability and low data representation. In order to achieve the above purpose, the present invention adopts the following technical scheme: The high-performance integrated circuit layout verification method comprises the steps of carrying out optimized coding on Manhattan directions, 45-degree edges and any angle edges through analysis of layout geometric characteristics, storing relative coordinate differences to obtain layout data with high compression ratio, dividing the layout into zones with balanced loads by utilizing layout density analysis and machine learning prediction and combining data locality and a buffer optimization strategy to obtain optimized parallel computing units, carrying out real-time monitoring on system resources and task states and combining a work stealing algorithm and data affinity scheduling to achieve multithread dynamic task allocation to obtain an efficient utilization computing resource allocation scheme, converting DRC rules into a graphical node structure, applying a common sub-expression elimination and operation fusion strategy to obtain a rule execution dependency graph, integrating SIMD instruction set to accelerate geometric calculation and combining a layered memory architecture and a prefetching mechanism to reduce memory access delay to obtain a low-memory occupied efficient data processing flow, and carrying out incremental updating and multi-condition query of an error database and combining Web real-time rendering and AI error classification to obtain an interactive verification report supporting collaborative review. Further, the method comprises the steps of adopting a depth analysis method for the layout geometric characteristics, extracting relative coordinate differences among adjacent vertexes to serve as a coding basis by identifying distribution rules of the Manhattan direction edges, the 45-degree direction edges and any angle edges, respectively adopting direction bit and length bit com