CN-122021543-A - Method, device, equipment and medium for detecting connection line design rule of quantum chip layout

CN122021543ACN 122021543 ACN122021543 ACN 122021543ACN-122021543-A

Abstract

The invention discloses a method, a device, equipment and a medium for detecting a connection line design rule of a quantum chip layout, which relate to the technical field of computers and comprise the steps of preprocessing connection line related data in the quantum chip layout design based on a quantum chip layout design tool to determine a target model training set; after integrating the target artificial intelligent large model into a quantum chip layout design tool, detecting the design rule of connecting wires in the initial quantum chip layout output by the quantum chip layout design tool based on the target artificial intelligent large model to obtain a model output result so as to determine whether to design and optimize the initial quantum chip layout. The invention can aim at the quantum chip design, and improve the automation, the efficiency and the accuracy of the detection of the design rule of the connecting wire.

Inventors

YU HONGZHEN
LI YANZHEN
XUE CHANGQING

Assignees

山东云海国创云计算装备产业创新中心有限公司

Dates

Publication Date: 20260512
Application Date: 20260228

Claims (10)

1. A method for detecting a connection line design rule of a quantum chip layout is characterized by comprising the following steps: Collecting connection line related data in the quantum chip layout design based on a quantum chip layout design tool, and preprocessing the connection line related data to determine a target model training set; Constructing an initial artificial intelligence large model based on a preset deep learning frame, and training the initial artificial intelligence large model by utilizing the target model training set and a regularization technology to obtain a target artificial intelligence large model for completing training; After integrating the target artificial intelligent large model into the quantum chip layout design tool, detecting the design rule of connecting lines in the initial quantum chip layout output by the quantum chip layout design tool based on the target artificial intelligent large model so as to determine a connecting line detection result; and determining a model output result based on the target artificial intelligence large model and the connecting line detection result so as to determine whether to perform design optimization on the initial quantum chip layout by utilizing the model output result.
2. The method for detecting connection line design rules of a quantum chip layout according to claim 1, wherein the collecting connection line related data in the quantum chip layout design based on the quantum chip layout design tool and preprocessing the connection line related data to determine a target model training set comprises: Collecting relevant data of connecting wires in the quantum chip layout design based on a quantum chip layout design tool, wherein the relevant data of the connecting wires comprise position coordinates, length and width; based on a preset data cleaning strategy, identifying invalid data of the related data of the connecting line to determine a first data identification result, wherein the invalid data is incomplete or data with wrong format; processing the connecting wire related data based on the first data identification result to determine first processed data; Based on the preset data cleaning strategy, identifying abnormal data of the first processed data to determine a second data identification result; processing the first processed data based on the second data identification result to determine second processed data; performing format conversion on the second processed data based on a preset data format to determine converted data; and determining a target model training set based on the converted data.
3. The method for detecting connection line design rules of a quantum chip layout according to claim 1, wherein the constructing an initial artificial intelligence large model based on a preset deep learning frame, and training the initial artificial intelligence large model by using the target model training set and a regularization technique, comprises: acquiring a preset deep learning frame; determining a framework design result based on a preset model framework design strategy; Determining an initial artificial intelligence large model based on the preset deep learning framework and the architecture design result, wherein the initial artificial intelligence large model comprises an input layer, a hidden layer and an output layer, and the hidden layer comprises a cyclic neural network, a converter and an activation function; Triggering training operation corresponding to the initial artificial intelligent large model based on the target model training set and regularization technology; in the process of executing the training operation, for any training round, model parameter updating is carried out on the trained large model of the current round by minimizing a target loss function and combining a back propagation algorithm so as to determine an updated large model; and executing model training of the next training round based on the updated large model, the target model training set and the regularization technology until a preset training termination condition is met, so as to obtain a target artificial intelligent large model.
4. A method for detecting connection line design rules of a quantum chip layout according to any one of claims 1 to 3, wherein the detecting the design rules of connection lines in the initial quantum chip layout output by the quantum chip layout design tool based on the target artificial intelligence large model comprises: When the quantum chip layout design tool triggers the quantum chip layout design operation, the corresponding initial quantum chip layout is used as the model input data of the target artificial intelligent large model; extracting characteristic information of a connecting wire from the initial quantum chip layout based on the target artificial intelligence large model to determine a characteristic information extraction result, wherein the characteristic information of the connecting wire comprises spatial characteristic information which comprises shape information and position relation information of the connecting wire; Determining the characteristic representation of each connecting line based on the target artificial intelligence large model, a forward propagation algorithm and the characteristic information extraction result; Inputting the characteristic representation to a preset classifier based on the target artificial intelligence large model; Analyzing the category probability of each connecting line based on the preset classifier and the characteristic representation to determine a category analysis result corresponding to each connecting line; And judging whether each connecting wire in the initial quantum chip layout accords with the current design rule based on the target artificial intelligent large model and the category analysis result so as to determine a connecting wire detection result.
5. The method for detecting a connection line design rule of a quantum chip layout according to claim 4, wherein analyzing the category probability of each connection line based on the preset classifier and the feature representation to determine a category analysis result corresponding to each connection line comprises: determining a connection line length detection result based on the preset classifier, the feature representation and a preset connection line length threshold; Determining a connection line width detection result based on the preset classifier, the feature representation and a preset connection line width threshold; determining a connection line spacing detection result based on the preset classifier, the feature representation and a preset connection line spacing threshold; determining a connecting wire resistance detection result based on the preset classifier, the characteristic representation and a preset connecting wire resistance threshold value; And determining a category analysis result corresponding to each connecting wire based on the preset classifier, the connecting wire length detection result, the connecting wire width detection result, the connecting wire spacing detection result and the connecting wire resistance detection result.
6. The method for detecting connection line design rules of a quantum chip layout according to claim 4, wherein the determining whether each connection line in the initial quantum chip layout meets the current design rules based on the target artificial intelligence large model and the category analysis result, comprises: Aiming at any connecting line in the initial quantum chip layout, if the corresponding category analysis result shows that the category with the highest probability is the first category, determining that the current connecting line accords with the current design rule; And if the corresponding category analysis result shows that the category with the highest probability is the second category, determining that the current connecting line does not accord with the current design rule.
7. The method for detecting connection line design rules of a quantum chip layout according to claim 6, wherein determining a model output result based on the target artificial intelligence large model and the connection line detection result comprises: If the connection line detection result indicates that a target connection line which does not accord with the current design rule exists in the initial quantum chip layout, determining a connection line optimization suggestion corresponding to the target connection line based on the target artificial intelligent large model and the category analysis result corresponding to the target connection line; and determining a model output result based on the connection line optimization suggestion and the connection line detection result.
8. A connection line design rule detection device of a quantum chip layout is characterized by comprising: The data collection module is used for collecting relevant data of connecting wires in the quantum chip layout design based on the quantum chip layout design tool, and preprocessing the relevant data of the connecting wires to determine a target model training set; The large model training module is used for constructing an initial artificial intelligent large model based on a preset deep learning frame, and training the initial artificial intelligent large model by utilizing the target model training set and a regularization technology to obtain a target artificial intelligent large model which is trained; the connecting wire detection module is used for detecting the design rule of connecting wires in the initial quantum chip layout output by the quantum chip layout design tool based on the target artificial intelligent large model after integrating the target artificial intelligent large model into the quantum chip layout design tool so as to determine a connecting wire detection result; and the result output module is used for determining a model output result based on the target artificial intelligent large model and the connecting line detection result so as to determine whether to perform design optimization on the initial quantum chip layout by utilizing the model output result.
9. An electronic device, comprising: A memory for storing a computer program; A processor for executing the computer program to implement the steps of the connection line design rule detection method of a quantum chip layout according to any one of claims 1 to 7.
10. A computer readable storage medium, wherein a computer program is stored on the computer readable storage medium, and the computer program when executed by a processor implements the steps of the method for detecting the connection line design rule of the quantum chip layout according to any one of claims 1 to 7.

Description

Method, device, equipment and medium for detecting connection line design rule of quantum chip layout Technical Field The invention relates to the technical field of computers, in particular to a method, a device, equipment and a medium for detecting a connecting wire design rule of a quantum chip layout. Background In recent years, EDA (electronic design automation ) online platforms have become an indispensable tool for electronic design. However, for quantum chip design, as the traditional layout design tool mainly adopts a rule-based method when connecting lines are designed in the layout, the layout is checked one by one through predefining a series of rules, but when a high-complexity and large-scale integrated circuit such as a quantum chip is processed, the problems of low detection efficiency, easy error, difficult adaptation to complex rule change and the like exist. In addition, with the continuous development of quantum chip design, the optimization requirement on the connection line design rule detection algorithm is higher and higher, and thus the traditional layout design tool cannot meet the requirements. Therefore, how to improve the efficiency and accuracy of the detection of the connection line design rule for the quantum chip design and to enhance the flexibility and expandability of the quantum chip design is a problem that needs to be solved by those skilled in the art. Disclosure of Invention The embodiment of the invention aims to provide a method, a device, equipment and a medium for detecting a connecting wire design rule of a quantum chip layout, which can solve the problems of how to improve the efficiency and the accuracy of detecting the connecting wire design rule for quantum chip design and enhance the flexibility and the expandability of the quantum chip design. The specific scheme is as follows: in a first aspect, the present invention provides a method for detecting a connection line design rule of a quantum chip layout, including: Collecting connection line related data in the quantum chip layout design based on a quantum chip layout design tool, and preprocessing the connection line related data to determine a target model training set; constructing an initial artificial intelligence large model based on a preset deep learning frame, and training the initial artificial intelligence large model by utilizing a target model training set and a regularization technology to obtain a target artificial intelligence large model for completing training; After integrating the target artificial intelligent large model into a quantum chip layout design tool, detecting design rules of connecting lines in the initial quantum chip layout output by the quantum chip layout design tool based on the target artificial intelligent large model so as to determine a connecting line detection result; And determining a model output result based on the target artificial intelligence large model and the connecting wire detection result so as to determine whether to perform design optimization on the initial quantum chip layout by using the model output result. Optionally, based on the quantum chip layout design tool, collecting connection line related data in the quantum chip layout design, and preprocessing the connection line related data to determine the target model training set includes: Collecting relevant data of connecting wires in the quantum chip layout design based on a quantum chip layout design tool, wherein the relevant data of the connecting wires comprise position coordinates, length and width; Based on a preset data cleaning strategy, identifying invalid data of the related data of the connecting line to determine a first data identification result; processing the connecting wire related data based on the first data identification result to determine first processed data; based on a preset data cleaning strategy, carrying out abnormal data identification on the first processed data so as to determine a second data identification result; processing the first processed data based on the second data identification result to determine second processed data; performing format conversion on the second processed data based on a preset data format to determine converted data; Based on the converted data, a target model training set is determined. Optionally, constructing an initial artificial intelligence large model based on a preset deep learning framework, and training the initial artificial intelligence large model by using a target model training set and a regularization technology, including: acquiring a preset deep learning frame; determining a framework design result based on a preset model framework design strategy; Determining an initial artificial intelligent large model based on a preset deep learning frame and a framework design result, wherein the initial artificial intelligent large model comprises an input layer, a hidden layer and an output layer, and the hidden layer compr