CN-122021545-A - Automatic generation method, system, medium, program and electronic terminal of memory architecture

Abstract

The disclosure provides an automatic generation method, system, medium, program and electronic terminal of a memory architecture, wherein at least one candidate memory macro unit meeting matching conditions is searched and extracted from a process library file according to theoretical process parameters and theoretical specifications of a target memory in a demand information table, and at least one target memory architecture scheme formed by one or more candidate memory macro units is determined based on a preset generation rule. Therefore, errors caused by human factors such as interface mismatch or signal collision are avoided, the efficiency is high, and the labor cost and the time cost of chip debugging and design are substantially reduced.

Inventors

• Request for anonymity
• Request for anonymity

Assignees

• 上海光羽芯辰科技有限公司

Dates

Publication Date

20260512

Application Date

20260408

Claims (10)

1. 1. An automatic generation method of a memory architecture, comprising: acquiring a process library file and a demand information table of a target memory; According to the theoretical process parameters and theoretical specifications of the target memory in the demand information table, at least one candidate storage macro unit meeting the matching conditions is searched and extracted from the process library file, wherein the candidate storage macro unit meeting the matching conditions means that the calibration process parameters and the calibration specifications of the candidate storage macro unit meet the requirements of the theoretical process parameters and the theoretical specifications of the target memory; Determining at least one target memory architecture scheme formed by one or more candidate memory macro units based on a preset generation rule, wherein the generation rule comprises that performance parameters of the architecture as a whole are calculated back to obtain corresponding actual process parameters and actual specifications, the actual process parameters and the actual specifications meet the requirements of the theoretical process parameters and the theoretical specifications, the calibration specifications and the actual specifications do not comprise bit width and depth.
2. 2. The method for automatically generating a memory architecture according to claim 1, wherein when the plurality of candidate memory macro units are spliced into the target memory architecture, the generation rule further comprises at least one constraint condition that the same type of splicing priority principle is followed when the candidate memory macro units are spliced, the width splicing priority principle is followed when the candidate memory macro units are spliced, the signal fan-out corresponding to the total bit width of the target memory architecture does not exceed a preset maximum fan-out threshold value, the logic level corresponding to the total depth of the target memory architecture does not exceed a preset maximum logic level threshold value, and the physical aspect ratio of the target memory architecture does not exceed a preset proportional range.
3. 3. The method for automatically generating a memory architecture according to claim 1, wherein the generation rule further comprises a plurality of preference conditions, and the method for determining at least one target memory architecture scheme composed of one or more candidate memory macro-cells comprises: On the premise of meeting the theoretical technological parameters and theoretical specifications, generating a plurality of target memory initial architecture schemes; mapping each preference condition into each corresponding fitness function; based on a non-dominant ordering genetic algorithm, iteratively evolving each initial architecture scheme and scoring the initial architecture scheme according to the fitness function in the evolution process so as to screen a candidate architecture set at the pareto optimal boundary; at least one initial architectural solution is screened from the candidate architectural set as a target memory architectural solution.
4. 4. The method of claim 3, wherein the preference condition comprises at least one of read/write dynamic power consumption, static leakage power consumption, critical path delay, physical aspect ratio, and wiring congestion.
5. 5. The method according to claim 1, wherein after determining at least one target memory architecture scheme composed of one or more candidate memory macro units, generating a corresponding file list according to the target memory architecture scheme, invoking a compiling tool to compile and verify the file list, and reserving the architecture scheme passing the compiling and verifying as a final target memory architecture scheme.
6. 6. The method of claim 1, wherein the theoretical specification, the calibration specification, and the actual specification include at least one of clock frequency, read-write delay, dynamic power consumption, static power consumption, physical area, operating voltage, and operating temperature.
7. 7. An automatic generation method system of a memory architecture, comprising: The information acquisition module is used for acquiring the process library file and a demand information table of the target memory; The candidate storage macro unit matching module is used for searching and extracting at least one candidate storage macro unit which accords with the matching condition from the process library file according to the theoretical process parameters and the theoretical specifications of the target memory in the demand information table, wherein the candidate storage macro unit accords with the matching condition, namely that the calibration process parameters and the calibration specifications of the candidate storage macro unit meet the requirements of the theoretical process parameters and the theoretical specifications of the target memory; The architecture scheme generating module is used for determining at least one target memory architecture scheme formed by one or more candidate memory macro units based on a preset generating rule, wherein the generating rule comprises that performance parameters of the architecture as a whole are calculated back to obtain corresponding actual process parameters and actual specifications, the actual process parameters and the actual specifications meet the requirements of the theoretical process parameters and the theoretical specifications, the calibration specifications and the actual specifications do not comprise bit widths and depths.
8. 8. A computer readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the method of any of claims 1-6.
9. 9. A computer program product comprising computer program code embodied therein, which when run on a computer causes the computer to carry out the method according to any of claims 1-6.
10. 10. An electronic terminal comprising a memory, a processor and a computer program stored on the memory, characterized in that the processor executes the computer program to implement the method of any of claims 1-6.

Description

Automatic generation method, system, medium, program and electronic terminal of memory architecture Technical Field The present disclosure relates to the field of chip design and manufacturing, and in particular, to an automatic generation method, system, medium, program and electronic terminal for a memory architecture. Background In the chip design and manufacturing process, a chip design manufacturer often needs to splice together a plurality of memory macro units provided by a wafer foundry (such as station power accumulation, central core international, etc.), so as to customize a chip with specific performance or function, thereby meeting the use requirements of specific application scenes. Since the concatenation of memory macro-cells involves a large number of complex mathematical calculations and logic designs, the traditional manual concatenation approach is inefficient and error-prone. In the design process, even a fine bit width calculation error or pin error can cause serious interface mismatch or signal conflict, and because the bottom layer error is hidden, the later investigation is often like a sea fishing needle, thus greatly increasing the debugging complexity and more likely causing the stagnation of the whole design progress. In addition, the development period of the chip is often longer, and under the current complex international situation, due to market fluctuations, supply chain policy adjustment or geopolitical changes, an emergency situation that the chip design link goes to half but is forced to replace the wafer foundry often occurs. The manufacturing equipment and the preset physical rules used by different wafer factories and different process nodes (such as 6nm and 12 nm) are different (that is, the process limitations have significant differences), so that the memory macro units processed by each wafer factory have large differences in physical specifications (such as length and width dimensions and pin arrangement) and performance characteristics (such as working voltage, reading and writing speed and power consumption level) and are not uniform. Therefore, when the wafer foundry is replaced, the splicing scheme is often required to be redesigned, the designed splicing scheme and packaging codes consume weeks or even months before the splicing scheme and packaging codes are instantly invalidated, a designer has to re-determine the splicing scheme from scratch and rewrite all codes according to the condition of the source of the new wafer foundry, the labor and time cost of repeated labor are extremely high, and the marketing progress of chip products is seriously tired. Disclosure of Invention In view of the foregoing drawbacks of the prior art, an object of the present disclosure is to provide an automatic generation method, system, medium, program and electronic terminal of a memory architecture, for solving the foregoing problems. The first aspect of the disclosure provides an automatic generation method of a memory architecture, which comprises the steps of obtaining a process library file and a demand information table of a target memory, retrieving and extracting at least one candidate memory macro unit meeting matching conditions in the process library file according to theoretical process parameters and theoretical specifications of the target memory in the demand information table, wherein the candidate memory macro unit meets the matching conditions, namely, the calibration process parameters and the calibration specifications of the candidate memory macro unit meet the requirements of the theoretical process parameters and the theoretical specifications of the target memory, determining at least one target memory architecture scheme formed by one or more candidate memory macro units based on a preset generation rule, and carrying out performance parameter back calculation on the architecture as a whole to obtain corresponding actual process parameters and actual specifications, wherein the actual process parameters and the actual specifications meet the requirements of the theoretical process parameters and the theoretical specifications, and the calibration specifications and the actual specifications do not comprise bit widths and depths. In some embodiments of the present disclosure, when the plurality of candidate storage macro-units are spliced into the target memory architecture, the generation rule further includes at least one constraint condition that a similar splicing priority principle is followed when the target memory architecture is spliced, a width splicing priority principle is followed when the target memory architecture is spliced, a signal fan-out corresponding to a total bit width of the target memory architecture does not exceed a preset maximum fan-out threshold, a logic progression corresponding to a total depth of the target memory architecture does not exceed a preset maximum logic progression threshold, and a physical aspect ratio of t