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CN-122021570-A - Chip design document intelligent generation system driven by multilayer LoRA fine tuning

CN122021570ACN 122021570 ACN122021570 ACN 122021570ACN-122021570-A

Abstract

The invention relates to an intelligent generation system of a chip design document driven by multilayer LoRA fine tuning. The system takes a hardware description language code as input, and parallelly executes two processing flows, namely, firstly, inputting the hardware description language code into a large model subjected to domain fine adjustment, reasoning to generate multi-layer semantic text information containing a module structure, behavior logic and design intention, secondly, carrying out grammar analysis on the hardware description language code to generate intermediate representation, and rendering based on the intermediate representation to obtain a structure diagram, a state transition diagram and a time sequence diagram. And finally, injecting the generated text and image into the multi-mode large model according to a predefined document template, integrating and outputting a complete chip design document, and evaluating the text quality and the picture quality of the generated document. The invention obviously improves the design efficiency of users and provides a high-reliability solution for the automatic generation of chip design documents.

Inventors

  • YU LE
  • WANG YUANWEN

Assignees

  • 北京工商大学

Dates

Publication Date
20260512
Application Date
20260305

Claims (10)

  1. 1. The intelligent chip design document generating system driven by the multilayer LoRA fine tuning is characterized by comprising the following steps: (1) taking Hardware Description Language (HDL) codes to be processed as input, and executing the step (2) and the step (3) in parallel; (2) Inputting the HDL codes into a domain big model, and reasoning to generate multi-layer semantic text information containing module structure semantics, behavior logic semantics and design intention semantics. The large domain model is a model which is pre-trained and subjected to domain fine adjustment; (3) Carrying out grammar analysis on the HDL codes, processing the HDL codes through Yosys to generate a unified Intermediate Representation (IR), configuring a plurality of traversers to analyze the IR output description files, and rendering a structure diagram, a state transition diagram and a time sequence diagram based on the files; (4) Injecting the text obtained in the step (2) and the image obtained in the step (3) into a multi-mode large model according to a predefined document template by adopting a prompt word strategy, and integrating and outputting a complete chip design document; (5) And (3) respectively evaluating the text quality and the picture quality of the generated document in the step (4), and outputting a comprehensive quality evaluation result. The method comprises the steps of calculating the similarity between a text part and a reference document, verifying whether a description file can be successfully rendered by a picture part, and taking two results as core indexes to evaluate the generation quality of a system.
  2. 2. The method according to claim 1, wherein the training method of the domain big model is characterized by comprising the steps of: (1) Cleaning and semantically labeling the collected HDL code data to obtain a training data set containing multiple layers of semantic information; (2) Based on the training data set, performing field adaptation training on the general large model by adopting LoRA fine tuning technology, wherein a plurality of layers of independent LoRA adapters are configured to be used for training different semantic layers respectively; (3) Integrating the multilayer LoRA adapter obtained in the step (2) into a unified domain large model, so that the domain large model can generate corresponding multilayer semantic text information based on the input HDL code.
  3. 3. The method of claim 1, wherein the plurality of specialized traversers employed in step (3) comprises: (1) The construction diagram traverser extracts a module instance tree, a signal connection relation and an assignment dependence, outputs a DOT file and obtains a construction diagram through rendering; (2) The state machine graph traversing device extracts the state nodes, the transition conditions and the state labels, outputs DOT files and obtains a state transition graph through rendering; (3) The time sequence diagram traverser extracts clock waveforms, reset sequences, register update events and handshake signal modes, outputs a JSON format file and obtains a time sequence diagram through rendering.
  4. 4. The method of claim 1, wherein the predefined document template used in step (4) is a structured document template for defining a chapter sequence of the generated document and a content type corresponding to each chapter. Wherein the document template includes the following sections: (1) A module function summary describing the overall function of the target module; (2) The input/output interface definition is used for explaining the port and signal relation of the module and synchronously embedding the structural diagram in the section; (3) The time sequence behavior description is used for describing time sequence logic or state machine behavior of the module and synchronously embedding a state transition diagram in the section; (4) Application scenario descriptions to illustrate typical applications or design constraints of the module; (5) And the standard code is used for displaying code content corresponding to the module and synchronously embedding a timing diagram in the section.
  5. 5. The method according to claim 1, wherein the evaluation method of step (5) specifically comprises: (1) The text quality assessment comprises the steps of calculating and generating the semantic matching degree of a document and a reference document by adopting a semantic similarity algorithm based on a pre-training language model, respectively giving preset weights to the semantic information of the L1 layer, the L2 layer and the L3 layer, and weighting to obtain a comprehensive text score; (2) Image quality verification, namely automatically executing image rendering in an isolated rendering environment, and evaluating the rendering success rate and the integrity of a structural diagram and a state transition diagram and the waveform logic precision of a timing diagram; and the text score and the image score are subjected to weighted fusion to obtain a comprehensive quality score which is used for judging whether the generated document reaches a preset quality standard.
  6. 6. The training method of claim 2, wherein the semantic annotation of the training dataset in step (1) comprises: (1) L1 layer label injection molding block name, port direction, port bit width, parameter definition, signal statement and instantiation relation; (2) The L2 layer marks sequential logic, triggering conditions and reset logic; (3) The L3 layer is based on L1 and L2 layer information and combines hardware design specifications to mark functional positioning, performance targets, key design logic and typical application scenes of the module.
  7. 7. The training method of claim 2, wherein the multi-layered LoRA adapter of step (2) comprises: (1) An L1 layer adapter LoRA _Structure for training output L1 semantics based on HDL code; (2) The L2 layer adapter LoRA _Behavior shares a base model weight space with LoRA _struct and is used for training and outputting L2 semantics; (3) The L3 layer adapter LoRA _Intent fuses the training weights of LoRA _Structure and LoRA _Behavir before training, and trains and outputs L3 semantics based on the fusion weights and HDL codes.
  8. 8. A computer readable storage medium having stored thereon a computer program which when executed by a processor implements the method of any of claims 1 to 7.
  9. 9. A computer device comprising a memory, a processor and a program stored in the memory and executable by the processor, wherein the program when executed implements the method of any one of claims 1 to 7.
  10. 10. A computer program product comprising a computer program which, when executed by a processor, implements the method of any of claims 1 to 7.

Description

Chip design document intelligent generation system driven by multilayer LoRA fine tuning Technical Field The invention relates to the technical field of integrated circuit design automation (EDA) and artificial intelligence crossing, in particular to a chip design document automatic generation system based on a large model. Background In the chip design flow, with the expansion of the chip scale, the demand of the matched design document is rapidly increased. However, the conventional document writing is still highly dependent on manpower, so that the efficiency is low, and the overall engineering progress is seriously delayed. Therefore, an automatic generation method is needed to improve efficiency and reduce cost. The prior art (such as CN 121031542A) proposes an automatic chip document generation system, which extracts texts, tables, pictures and relation trees by analyzing chip files through rules, automatically generates documents by combining templates, and supports security level filtering and template expansion. However, the scheme still highly depends on fixed rules, cannot effectively extract design intent, is difficult to carry out reverse function interpretation on complex HDL codes, causes insufficient description depth of generated documents, is difficult to unify standards, and has difficulty in meeting the requirements of modern large-scale chip projects on high-quality design documents. Therefore, a chip design document automatic generation system based on a large model is needed, the large model is introduced to perform multi-layer semantic extraction and multi-mode integration, documents with complete semantics and accurate structures can be automatically generated, charts are synchronously embedded, the design efficiency is improved, and the blank in the field of automation is filled. Disclosure of Invention The invention aims to overcome the defects of the prior art and provides a chip design document automatic generation system based on a large model. In order to achieve the above purpose, the invention provides a chip design document intelligent generation system driven by multi-layer LoRA fine tuning, which is characterized by comprising the following steps: (1) taking HDL codes to be processed as input, and executing the step (2) and the step (3) in parallel; (2) Inputting the HDL codes into a domain big model, and reasoning to generate multi-layer semantic text information containing module structure semantics, behavior logic semantics and design intention semantics. The large domain model is a model which is pre-trained and subjected to domain fine adjustment; (3) Carrying out grammar analysis on the HDL codes, processing the HDL codes through Yosys to generate unified IR, configuring a plurality of traversers to analyze the IR output description files, and rendering a structure diagram, a state transition diagram and a time sequence diagram based on the files; (4) Injecting the text obtained in the step (2) and the image obtained in the step (3) into a multi-mode large model according to a predefined document template by adopting a prompt word strategy, and integrating and outputting a complete chip design document; (5) And (3) respectively evaluating the text quality and the picture quality of the generated document in the step (4), and outputting a comprehensive quality evaluation result. The method comprises the steps of calculating the similarity between a text part and a reference document, verifying whether a code of the picture part can be successfully rendered and correctly displayed, and taking two results as core indexes to evaluate the generation quality of a system. Further, the training method of the domain big model comprises the following steps: (1) Cleaning and semantically labeling the collected HDL code data to obtain a training data set containing multiple layers of semantic information; (2) Based on the training data set, performing field adaptation training on the general large model by adopting LoRA fine tuning technology, wherein a plurality of layers of independent LoRA adapters are configured to be used for training different semantic layers respectively; (3) Integrating the multilayer LoRA adapter obtained in the step (2) into a unified domain large model, so that the domain large model can generate corresponding multilayer semantic text information based on the input HDL code. Further, the multiple dedicated traversers adopted in the step (3) of the chip design document intelligent generation system driven by the multi-layer LoRA fine tuning comprise: (1) The construction diagram traverser extracts a module instance tree, a signal connection relation and an assignment dependence, outputs a DOT file and obtains a construction diagram through rendering; (2) The state machine graph traversing device extracts the state nodes, the transition conditions and the state labels, outputs DOT files and obtains a state transition graph through rendering; (3) The ti