CN-122021748-A - Fault tree Boolean function equivalent mapping method based on untrained neural network

CN122021748ACN 122021748 ACN122021748 ACN 122021748ACN-122021748-A

Abstract

A failure tree Boolean function equivalent mapping method based on a training-free neural network relates to the field of failure tree analysis. In order to solve the problems that a Boolean function mapping structure in the prior art is unfavorable for parallel expansion, is limited in calculation efficiency and is difficult to realize on a high-parallel platform such as a GPU (graphics processing unit), the method provided by the invention generates topological structure data by analyzing a fault tree model, maps basic events, intermediate events and top events into neurons of an input layer, a hidden layer and an output layer respectively, builds a feed-forward network with fixed weight and bias, and defines a logic activation function in a node to realize Boolean logic propagation. The input layer receives the basic event state vector, outputs the top event result through forward propagation, and can realize large-scale Boolean function mapping on a parallel platform through a batch input matrix. The method is suitable for the tasks of reliability analysis, minimum cut-and-gather simplification, top event probability calculation, parallelization fault tree solving and the like of a large-scale complex system.

Inventors

DING MING
YANG YONGYONG
CAO XIAXIN
GUO ZEHUA
MENG ZHAOMING
WANG YANKAI
HAO XIAOTIAN

Assignees

哈尔滨工程大学

Dates

Publication Date: 20260512
Application Date: 20251223

Claims (10)

1. The fault tree Boolean function equivalent mapping method based on the untrained neural network is characterized by comprising the following steps of: analyzing the input fault tree model, extracting connection information among basic events, intermediate events, logic gates and top events, establishing an event level and connection relation and generating fault tree topological structure data; mapping basic events, intermediate events and top events in the fault tree into neurons of an input layer, a hidden layer and an output layer respectively according to the topological structure data, and establishing corresponding connection relations to form a neural network topology with equivalent structure; constructing a non-training feedforward network structure based on the neural network topology, setting a connection weight to be a fixed value of one, and setting a bias to be zero to obtain a fixed calculation structure for Boolean logic propagation; Defining an activation function according to the type of a logic gate in a neuron node of the computing structure, wherein the AND gate is a logic AND operation in which all inputs are output as one, the OR gate is a logic OR operation in which any input is output as one, and a neural network with a Boolean logic mapping function is obtained; Inputting an input vector representing a basic event state into the neural network, and obtaining a top event Boolean output or a probabilistic output result through forward propagation; And forming a batch of input matrixes by a plurality of input vectors, and simultaneously executing forward propagation on a parallel computing platform to obtain a plurality of top event corresponding result sets so as to realize the parallel mapping of the fault tree Boolean function.
2. The method for equivalent mapping of a fault tree boolean function based on a training-free neural network according to claim 1, characterized in that the logic gate type and the event dependency relationship are automatically identified by a semantic parsing algorithm, and an event relationship table conforming to the topological order is generated according to the node level.
3. The method for equivalent mapping of a fault tree boolean function based on a training-free neural network according to claim 1, characterized in that the topology of the neural network is completely equivalent to the logical structure of the fault tree in level by establishing a node index table and defining a directed connection relationship.
4. The method of claim 1, wherein all connection weights are set to one, the bias is zero, and the network parameters are kept frozen to avoid back propagation of the training process and to ensure certainty and interpretability of the computational logic.
5. The method of claim 1, further comprising the step of expanding the activation function to a continuously conductive form to enable the input signal to take a real value between zero and one to achieve an integrated mapping of boolean logic and probability logic.
6. The method for performing a training-free neural network-based fault tree boolean function equivalent mapping according to claim 1, further comprising the step of implementing a synchronous calculation of a plurality of fault combining scenarios by setting different sample input sequences at the input layer to form a matrix batch input.
7. The utility model provides a fault tree boolean function equivalent mapping device based on no training neural network which characterized in that includes: Analyzing the input fault tree model, extracting connection information among basic events, intermediate events, logic gates and top events, establishing an event level and connection relation and generating fault tree topological structure data; According to the topological structure data, mapping basic events, intermediate events and top events in the fault tree into neurons of an input layer, a hidden layer and an output layer respectively, and establishing corresponding connection relations to form a module of a neural network topology with equivalent structure; based on the neural network topology, constructing a non-training feedforward network structure, setting a connection weight as a fixed value of one, and setting a bias as zero to obtain a module of a fixed calculation structure for Boolean logic propagation; in the neuron node of the computation structure, an activation function is defined according to the type of a logic gate, an AND gate is corresponding to logic AND operation in which all inputs are output as one, an OR gate is corresponding to logic OR operation in which any input is output as one, and a module of the neural network with the Boolean logic mapping function is obtained; The module is used for inputting an input vector representing the state of the basic event into the neural network and obtaining a top event Boolean output or a probabilistic output result through forward propagation; And forming a batch of input matrixes by a plurality of input vectors, and simultaneously executing forward propagation on a parallel computing platform to obtain a plurality of top event corresponding result sets so as to realize the parallel mapping of the fault tree Boolean function.
8. Computer storage medium for storing a computer program, characterized in that the computer performs the method of claim 1 when the computer program is read by the computer.
9. A computer comprising a processor and a storage medium, characterized in that the computer performs the method of claim 1 when the processor reads a computer program stored in the storage medium.
10. Computer program product, as a computer program, characterized in that the method of claim 1 is implemented when the computer program is executed.

Description

Fault tree Boolean function equivalent mapping method based on untrained neural network Technical Field Relates to the field of fault tree analysis, in particular to a high-efficiency parallelization fault tree cut set solving method. Background Fault tree analysis (FTA for short) is a systematic, security analysis method for describing the causal relationship between system top events (typically system faults) and individual basic events (typically component failures) by logical structure. The method is characterized in that a Boolean logic function is utilized to express a failure mechanism of the system, so that quantitative calculation of system reliability, importance assessment and fault diagnosis are realized. In the traditional fault tree analysis, the evaluation of the boolean function is a core calculation process, and is commonly used for Minimum Cut Set (MCS) solving, top event probability calculation, importance analysis and the like. This process typically requires a logical propagation determination for a large number of basic event combinations. For example, in the stage of minimal cut set simplification, boolean decisions need to be performed one by one for each candidate cut set to verify whether partial events can still result in top events after culling. This means that in a large scale system containing thousands of basic events and hundreds of thousands of cutsets, the boolean function mapping operation can be invoked at high frequencies, which becomes a major performance bottleneck for the overall computational flow. In order to improve the Boolean propagation efficiency of the fault tree, researchers propose various acceleration algorithms. For example, a binary decision diagram (BDD, binary Decision Diagram) is adopted to represent a Boolean function, redundant logic calculation can be reduced through node sharing, solving efficiency is improved, for example, approximate estimation of top event probability is realized through random sampling based on probability analysis of a Monte Carlo method, the method is suitable for reliability evaluation of a complex system, and a learner tries to decompose a complex fault tree into a plurality of sub-modules through a modularized fault tree decomposition and sub-tree parallel calculation method so as to improve parallelism and expandability. However, although the BDD method is excellent in structural compactness, the BDD method is easy to cause node explosion (state explosion) problems when facing large-scale fault trees with deep hierarchy and complex logic, so that memory consumption is increased greatly, monte Carlo simulation has good universality, but Boolean propagation is still required to be performed sample by sample, parallel hardware performance is difficult to fully develop, and modularized decomposition can realize parallel partially, but the overall acceleration effect is limited due to strong logic relevance among different modules. In addition, the existing boolean mapping method is mostly based on a serial implementation mode of recursive call or logic gate traversal, has irregular logic structure, and is difficult to realize efficient calculation on parallel architectures such as GPU, TPU and the like. In recent years, with the development of artificial intelligence and parallel computing technology, some researches have been attempted to introduce a neural network model into system reliability analysis for learning the correspondence between system states and top events. However, the methods depend on supervised training data, require a large number of samples and training processes to achieve high Boolean function fitting accuracy, have poor model interpretability, and are not suitable for fault tree analysis scenes with extremely high safety requirements and definite logic relations. In summary, the prior art has the defects that the Boolean function mapping structure is unfavorable for parallel expansion, the computing efficiency is limited, the logical equivalence and the interpretability cannot be considered, and the Boolean function mapping structure is difficult to be directly and efficiently realized on a high-parallel platform such as a GPU. Disclosure of Invention In order to solve the defects that the Boolean function mapping structure in the prior art is unfavorable for parallel expansion, has limited calculation efficiency, cannot consider both logic equivalence and interpretability and is difficult to realize on a high-parallel platform such as a GPU (graphic processing unit), the technical scheme provided by the invention is as follows: a fault tree Boolean function equivalent mapping method based on a training-free neural network comprises the following steps: analyzing the input fault tree model, extracting connection information among basic events, intermediate events, logic gates and top events, establishing an event level and connection relation and generating fault tree topological structure data; mapp