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CN-122021750-A - Lightweight CMOS LIF neuron circuit

CN122021750ACN 122021750 ACN122021750 ACN 122021750ACN-122021750-A

Abstract

The invention relates to the technical field of LIF neuron circuits, in particular to a lightweight CMOS LIF neuron circuit which comprises a first inverter, a second inverter and a film capacitor leakage device, wherein the first inverter judges whether input voltage reaches a threshold value and drives the second inverter to discharge in a pulse mode, the second inverter resets film potential after the pulse discharge, a drain electrode of the film capacitor leakage device is connected with an input current end as a film potential node, and parasitic capacitance of the film capacitor leakage device is used as film capacitance for integration. The LIF neuron circuit design method aims at solving the problems of complex structure, large area, high power consumption and the like existing in the existing LIF neuron circuit design.

Inventors

  • XU QUAN
  • WANG YIXUAN
  • WU HUAGAN
  • CHEN MO
  • WANG NING

Assignees

  • 常州大学

Dates

Publication Date
20260512
Application Date
20260121

Claims (9)

  1. 1. A lightweight CMOS LIF neuron circuit, comprising the steps of: a first inverter, a second inverter and a film capacitance leakage device, wherein, The first inverter judges whether the input voltage reaches a threshold value and drives the second inverter to pulse discharge; the second inverter resets the membrane potential after pulse discharge; The drain electrode of the film capacitor leakage device is used as a film potential node to be connected with the input current end, and the parasitic capacitance of the film capacitor leakage device is used as a film capacitance for integration.
  2. 2. The lightweight CMOS LIF neuron circuit of claim 1, wherein the CMOS LIF neuron circuit comprises: The PMOS transistor M 1 、M 3 and the NMOS transistor M 2 、M 4 、M 5 , wherein the common grid electrode of the M 1 、M 2 is connected with the drain electrode of the M 5 , the common grid electrode of the M 3 、M 4 is connected with the common drain electrode of the M 1 、M 2 , the common drain electrode of the M 3 、M 4 is connected with the grid electrode of the M 5 , and the source electrode of the M 5 is grounded.
  3. 3. The lightweight CMOS LIF neuron circuit of claim 2, wherein M 2 ,M 4 is model number M2SK926.
  4. 4. The lightweight CMOS LIF neuron circuit of claim 2, wherein M 1 ,M 3 is model number M2SJ136.
  5. 5. The lightweight CMOS LIF neuron circuit of claim 2, wherein M 5 is model M2SK703.
  6. 6. The lightweight CMOS LIF neuron circuit of claim 2, wherein the source voltage of M 1 is 2.11V.
  7. 7. The lightweight CMOS LIF neuron circuit of claim 2, wherein the source voltage of M 3 is 1.5V.
  8. 8. The lightweight CMOS LIF neuron circuit of claim 2, wherein the source voltage of M 2 is-1.5V.
  9. 9. The lightweight CMOS LIF neuron circuit of claim 2, wherein the source voltage of M 4 is-0.3V.

Description

Lightweight CMOS LIF neuron circuit Technical Field The invention relates to the technical field of LIF neuron circuits, in particular to a lightweight CMOS LIF neuron circuit. Background Among various neuron circuit models, LEAKY INTEGRATE-and-fire models become common pulse neuron models for realizing nerve morphology chips due to the advantages of simple structure, good expandability, high calculation efficiency and the like, and researches have shown that in order to realize large-scale SNN hardware in mobile and edge equipment, the neuron circuits need to be deeply optimized for area and power consumption, so that the design of ultra-low power consumption and ultra-small area light CMOS LIF neuron circuits is a key for breaking through the scale bottleneck of brain-like calculation chips. In order to reduce the power consumption, many traditional CMOS analog neuron circuits bias transistors in subthreshold areas to obtain extremely low peak power consumption, but subthreshold currents are very sensitive to process drift and temperature change, and as the process size is reduced, the subthreshold currents and parasitic effects are increased to possibly cause problems of poor process suitability, no reduction of power consumption, reverse rising and the like, research is also carried out on improving device characteristics by adopting an FDSOI process and back gate bias to reduce the power consumption, but a complex circuit structure and a plurality of control modules are usually needed, the area is increased and the dependence on a process platform is strong, in addition, a nano motor system (NEMS) device is adopted in some designs to realize near zero standby power consumption, but the NEMS switching speed is slow, the service life is limited, the manufacturing process is not mature, the area problem caused by an external capacitor cannot be eliminated, under the standard CMOS process, the area of the external capacitor is far larger than the area of the transistor, and the LIF neuron circuit design with simpler structure, smaller area and lower power consumption and easy integration is needed. Disclosure of Invention Aiming at the defects of the existing circuit, the LIF neuron circuit solves the problems of complex structure, large number of devices, large chip area, high power consumption and the like of the existing LIF neuron circuit. The technical scheme adopted by the invention is that the lightweight CMOS LIF neuron circuit comprises: a first inverter, a second inverter and a film capacitance leakage device, wherein, The first inverter judges whether the input voltage reaches a threshold value and drives the second inverter to pulse discharge; the second inverter resets the membrane potential after pulse discharge; The drain electrode of the film capacitor leakage device is used as a film potential node to be connected with the input current end, and the parasitic capacitance of the film capacitor leakage device is used as a film capacitance for integration. As a preferred embodiment of the present invention, the CMOS LIF neuron circuit comprises: The PMOS transistor M 1、M3 and the NMOS transistor M 2、M4、M5, wherein the common grid electrode of the M 1、M2 is connected with the drain electrode of the M 5, the common grid electrode of the M 3、M4 is connected with the common drain electrode of the M 1、M2, the common drain electrode of the M 3、M4 is connected with the grid electrode of the M 5, and the source electrode of the M 5 is grounded. As a preferred embodiment of the invention, M 2,M4 is model M2SK926. As a preferred embodiment of the invention, M 1,M3 is model M2SJ136. As a preferred embodiment of the invention, M 5 is model M2SK703. As a preferred embodiment of the present invention, the source voltage of M 1 is 2.11V. As a preferred embodiment of the present invention, the source voltage of M 3 is 1.5V. As a preferred embodiment of the invention, the source voltage of M 2 is-1.5V. As a preferred embodiment of the invention, the source voltage of M 4 is-0.3V. The invention has the beneficial effects that: 1. the circuit can complete the core functions of integration, leakage, threshold detection, pulse reset and the like of the membrane potential with a small number of transistors by reasonably combining and feeding back the CMOS inverter and a single NMOS device, and the chip area and the power consumption are obviously reduced. Drawings FIG. 1 is a schematic diagram of a circuit configuration of the present invention; FIG. 2 is a circuit simulation graph of input current versus discharge frequency; FIG. 3 is a graph of the results of numerical simulation of the relationship of input current to discharge frequency; FIG. 4 is a simulation result of a transient response waveform of a critical node voltage; FIG. 5 is a numerical simulation result of an engineering behavior model of a key node; FIG. 6 is a simulation result when a DC current is input to the circuit; FIG. 7 is a simulation re