CN-122022312-A - Power chip test optimization method and device, terminal equipment and storage medium

Abstract

The application relates to the technical field of chip testing, in particular to a power supply chip testing optimization method, a device, terminal equipment and a storage medium, wherein the method comprises the steps of collecting historical test data of a target power supply chip, and constructing time sequence data of each test item in the historical test data into a three-dimensional test tensor; the method comprises the steps of abstracting each test item into graph nodes, establishing edges representing physical connection based on a circuit netlist to form a dynamic space-time graph, carrying out multi-granularity weighted fusion on space-time combined features by sequentially applying a time attention mechanism, a graph attention mechanism and a feature attention mechanism to obtain space-time weighted attention features, calculating sensitivity indexes of each test item to environmental changes according to the space-time weighted attention features, generating a dynamic test sequence according to descending arrangement of the sensitivity indexes of each test item, and sending the dynamic test sequence to test equipment to execute test, so that the test efficiency of a power chip is optimized.

Inventors

• ZHOU HAIFENG
• DU RUONAN
• WANG ZILIANG
• Guo Yingkuan
• WEI NA
• YU SHUJUAN
• GAO HONG
• Cui Yate
• DUAN JIAHUI
• GUO YUHUI
• LIU YONGSHUN
• XIONG YUQING
• CHEN GUANGYAO
• ZHANG TAO
• FU JIAJIA
• SUN YIXUAN
• LU MENGNI

Assignees

• 奇瑞汽车股份有限公司

Dates

Publication Date

20260512

Application Date

20260127

Claims (10)

1. 1. A power chip test optimization method, comprising: Collecting historical test data of a target power supply chip, and constructing time sequence data of each test item in the historical test data into a three-dimensional test tensor; abstracting each test item into graph nodes, establishing edges representing physical connection based on a circuit netlist, and establishing statistical correlation edges based on dynamic association among each test item to form a dynamic space-time graph; processing the three-dimensional test tensor and the dynamic space-time diagram through a dynamic space-time diagram convolutional neural network to obtain space-time joint characteristics, and performing multi-granularity weighted fusion on the space-time joint characteristics to obtain space-time weighted attention characteristics; And according to the descending order of the sensitivity indexes of the test items, generating a dynamic test sequence, and sending the dynamic test sequence to test equipment for executing test.
2. 2. The power chip test optimization method according to claim 1, wherein the processing the three-dimensional test tensor and the dynamic space-time diagram through the dynamic space-time diagram convolutional neural network to obtain a space-time joint feature comprises: extracting the space characteristics of each dynamic space-time diagram and each time step of the three-dimensional test tensor through space diagram convolution operation; and carrying out one-dimensional convolution on the spatial features along the time dimension to extract the space-time joint features.
3. 3. The power chip test optimization method according to claim 1, wherein after the spatiotemporal weighted attention feature is obtained, further comprising: Inputting the space-time weighted attention characteristic into the dynamic space-time graph convolutional neural network, adding Laplacian noise or Gaussian noise into the dynamic space-time graph convolutional neural network based on a federal learning framework, and performing iterative training to update the dynamic space-time graph convolutional neural network.
4. 4. The power chip test optimization method according to claim 1, wherein the creating a dynamic time-space diagram based on the dynamic association between the test items to create statistically relevant edges comprises: and quantifying the dynamic association between the test items based on the Pelson correlation coefficient in the sliding time window to establish statistical correlation edges, and forming a dynamic time-space diagram.
5. 5. The power chip test optimization method according to claim 1, wherein after generating the dynamic test sequence, further comprising: And carrying out feasibility adjustment on the dynamic test sequence by combining the actual test resource constraint and the test dependency relationship to finally form an executable optimized test flow.
6. 6. The power chip test optimization method according to claim 1, further comprising introducing a physical information fusion layer in the dynamic space-time diagram convolutional neural network; The physical information fusion layer is used for encoding line impedance, euclidean distance among nodes and heat distribution parameters of the chip into a physical constraint matrix, and fusing the physical constraint matrix with the space-time combined features through feature crossing operation.
7. 7. The method of claim 1, wherein the historical test data comprises time series data of voltage, current, temperature and power consumption of a plurality of the test items.
8. 8. A power chip test optimizing apparatus, comprising: The data acquisition module is used for acquiring historical test data of the target power supply chip and constructing time sequence data of each test item in the historical test data into a three-dimensional test tensor; The space-time correlation module is used for abstracting each test item into graph nodes, establishing edges representing physical connection based on a circuit netlist, and establishing statistical correlation edges based on dynamic correlation among each test item to form a dynamic space-time graph; The model fusion module is used for processing the three-dimensional test tensor and the dynamic space-time diagram through a dynamic space-time diagram convolutional neural network to obtain space-time joint characteristics, and carrying out multi-granularity weighted fusion on the space-time joint characteristics to obtain space-time weighted attention characteristics; And the sequence generation module is used for calculating the sensitivity index of each test item to environmental change according to the time-space weighted attention characteristic, generating a dynamic test sequence according to the descending order of the sensitivity index of each test item, and transmitting the dynamic test sequence to test equipment for executing test.
9. 9. A terminal device, characterized in that it comprises a processor and a memory, the memory storing a computer program, the processor being adapted to execute the computer program to implement the power chip test optimization method according to any one of claims 1-7.
10. 10. A readable storage medium, characterized in that it stores a computer program which, when executed on a processor, implements the power chip test optimization method according to any one of claims 1-7.

Description

Power chip test optimization method and device, terminal equipment and storage medium Technical Field The present application relates to the field of chip testing technologies, and in particular, to a power chip testing optimization method, a device, a terminal device, and a storage medium. Background With the development of electronic equipment toward miniaturization, high performance and low power consumption, a power supply chip is used as a core power supply unit, and the reliability, stability and conversion efficiency of the power supply chip directly influence the operation quality of the whole system. Modern power chips often integrate multiple protection mechanisms (e.g., overvoltage, overcurrent, thermal shutdown), multiple output control, and complex switching topologies, resulting in unprecedented challenges in design verification and mass production testing stages. The current mainstream power chip test optimization flow generally adopts a mode of executing a plurality of independent test items in a serial fixed sequence, including but not limited to input voltage range test, load adjustment rate test, start-up time measurement, quiescent current detection, temperature drift calibration and the like. The method has the problem of low test efficiency, and because the number of test items is huge (up to tens of items), and most of tests are required to be repeatedly executed under different working modes and environmental conditions, the whole test period of a single chip is often up to several hours, and the production takt and yield are seriously restricted to be improved. Disclosure of Invention In view of the above, the embodiments of the present application provide a power chip test optimization method, apparatus, terminal device, and storage medium, which can effectively solve the problem of low efficiency. In a first aspect, an embodiment of the present application provides a power chip test optimization method, including: Collecting historical test data of a target power supply chip, and constructing time sequence data of each test item in the historical test data into a three-dimensional test tensor; abstracting each test item into graph nodes, establishing edges representing physical connection based on a circuit netlist, and establishing statistical correlation edges based on dynamic association among each test item to form a dynamic space-time graph; processing the three-dimensional test tensor and the dynamic space-time diagram through a dynamic space-time diagram convolutional neural network to obtain space-time joint characteristics, and performing multi-granularity weighted fusion on the space-time joint characteristics to obtain space-time weighted attention characteristics; And according to the descending order of the sensitivity indexes of the test items, generating a dynamic test sequence, and sending the dynamic test sequence to test equipment for executing test. In some embodiments, the processing the three-dimensional test tensor and the dynamic space-time graph through the dynamic space-time graph convolutional neural network to obtain a space-time joint feature includes: extracting the space characteristics of each dynamic space-time diagram and each time step of the three-dimensional test tensor through space diagram convolution operation; and carrying out one-dimensional convolution on the spatial features along the time dimension to extract the space-time joint features. In some embodiments, after the obtaining the spatiotemporal weighted attention feature, the method further includes: Inputting the space-time weighted attention characteristic into the dynamic space-time graph convolutional neural network, adding Laplacian noise or Gaussian noise into the dynamic space-time graph convolutional neural network based on a federal learning framework, and performing iterative training to update the dynamic space-time graph convolutional neural network. In some embodiments, the forming a dynamic space-time diagram based on the dynamic association between the test items to establish statistically relevant edges includes: and quantifying the dynamic association between the test items based on the Pelson correlation coefficient in the sliding time window to establish statistical correlation edges, and forming a dynamic time-space diagram. In some embodiments, after generating the dynamic test sequence, the method further includes: And carrying out feasibility adjustment on the dynamic test sequence by combining the actual test resource constraint and the test dependency relationship to finally form an executable optimized test flow. In some embodiments, the method further comprises introducing a physical information fusion layer in the dynamic space-time diagram convolutional neural network; The physical information fusion layer is used for encoding line impedance, euclidean distance among nodes and heat distribution parameters of the chip into a physical constraint matrix, and