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CN-122023293-A - Wafer defect detection method, equipment, medium and product

CN122023293ACN 122023293 ACN122023293 ACN 122023293ACN-122023293-A

Abstract

The application discloses a wafer defect detection method, equipment, medium and product, and relates to the technical field of semiconductor integrated circuits. The wafer defect detection method comprises the steps of carrying out defect scanning on a wafer to obtain a to-be-detected defect image of at least one to-be-detected defect position of the wafer, aligning the to-be-detected defect image with a chip design layout of the wafer to determine graphic features of the design layout graphic of the to-be-detected defect position, selecting a reference image generation model with adapted graphic features of the design layout graphic based on graphic feature conditions corresponding to a plurality of reference image generation models respectively, enabling different reference image generation models to correspond to different graphic feature conditions, converting the design layout graphic into a reference image based on the reference image generation model with adapted design layout graphic, and comparing the to-be-detected defect image of the to-be-detected defect position with the reference image to obtain a defect detection result.

Inventors

  • YAN CHANGLIAN
  • ZHANG SHENGRUI

Assignees

  • 东方晶源微电子科技(北京)股份有限公司

Dates

Publication Date
20260512
Application Date
20260116

Claims (10)

  1. 1. A method for detecting wafer defects, comprising: Performing defect scanning on a wafer to obtain a to-be-detected defect image of at least one to-be-detected defect position of the wafer; Aligning the defect image to be detected with the chip design layout of the wafer to determine the graphic characteristics of the design layout graphic of the defect position to be detected; Selecting a reference image generation model with the matched graphic features of the design layout graphics based on graphic feature conditions respectively corresponding to a plurality of reference image generation models, wherein different reference image generation models correspond to different graphic feature conditions; Generating a model based on the reference image adapted to the design layout graph, and converting the design layout graph into a reference image; and comparing the defect image to be detected of the defect position to be detected with the reference image to obtain a defect detection result.
  2. 2. The wafer defect detection method according to claim 1, wherein the selecting the reference image generation model adapted to the graphic features of the design layout graphic based on the graphic feature conditions respectively corresponding to the plurality of reference image generation models includes: Determining the graphic complexity of the design layout graph based on the graphic features of the design layout graph, matching the graphic complexity with the graphic complexity conditions respectively corresponding to a plurality of reference image generation models, and selecting the reference image generation model with the matched graphic complexity; Or alternatively Determining a design checking rule triggered by the design layout graph based on the graph characteristics of the design layout graph, matching the design checking rule with the design checking rule conditions corresponding to the plurality of reference image generating models respectively, and selecting the reference image generating model adapted by the design checking rule.
  3. 3. The method according to claim 2, wherein the plurality of reference image generation models includes a first reference image generation model that generates a reference image based on optical proximity correction and a second reference image generation model that generates a reference image based on hot spot simulation, and wherein a pattern complexity required by a pattern complexity condition corresponding to the first reference image generation model is lower than a pattern complexity required by a pattern complexity condition corresponding to the second reference image generation model.
  4. 4. The wafer defect detection method of claim 3, wherein, in the case where the design layout pattern is adapted to the first reference image generation model, converting the design layout pattern into a reference image based on the reference image generation model to which the design layout pattern is adapted, comprises: Performing optical proximity correction on the design layout graph to obtain a corrected mask graph; Calculating the light intensity distribution corresponding to the corrected mask pattern based on an optical model; Predicting a photoresist pattern based on the photoresist model and the light intensity distribution; performing etching compensation on the photoresist pattern based on an etching compensation rule to obtain an etched and compensated pattern; and performing etching simulation based on the pattern after etching compensation to obtain a reference image generated by the etching simulation.
  5. 5. The wafer defect detection method of claim 3, wherein, in the case where the design layout pattern is adapted to the second reference image generation model, converting the design layout pattern into a reference image based on the reference image generation model to which the design layout pattern is adapted, comprises: Performing optical proximity correction on the design layout graph to obtain a corrected mask graph; Calculating light intensity distribution corresponding to the corrected mask pattern based on a hot spot model, wherein the light intensity distribution comprises the light intensity distribution of a hot spot area; Predicting a photoresist pattern based on the photoresist model and the light intensity distribution; And performing etching simulation on the photoresist pattern based on the hot spot etching model to obtain a reference image generated by the etching simulation.
  6. 6. The method for inspecting a wafer defect according to any one of claims 1 to 5, wherein comparing the image of the defect to be inspected with the reference image to obtain a defect inspection result includes: Calculating the difference degree between the figure outline in the defect image to be detected and the figure outline in the reference image; Determining a difference threshold to be compared corresponding to the graphic features based on the graphic complexity corresponding to the graphic features, wherein a negative correlation is formed between the graphic complexity and the difference threshold to be compared; judging whether the difference degree exceeds a difference threshold to be compared corresponding to the graphic features; If yes, determining that the defect to be detected exists in the position of the defect; if not, determining that the defect to be detected does not exist in the position of the defect.
  7. 7. The method for inspecting a wafer defect according to any one of claims 1 to 5, wherein comparing the image of the defect to be inspected with the reference image to obtain a defect inspection result includes: performing image stitching on the defect images to be detected of a plurality of defect positions to be detected to obtain stitched defect images; Image stitching is carried out on the reference images of the defect positions to be detected, and a stitched reference image is obtained; and comparing the spliced defect image with the spliced reference image to obtain defect detection results of a plurality of defect positions to be detected.
  8. 8. An electronic device comprising a processor and a memory storing computer program instructions; The processor, when executing the computer program instructions, implements the wafer defect detection method as claimed in any one of claims 1-7.
  9. 9. A computer readable storage medium, wherein computer program instructions are stored on the computer readable storage medium, which when executed by a processor, implement the wafer defect detection method according to any of claims 1-7.
  10. 10. A computer program product, characterized in that instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the wafer defect detection method according to any of claims 1-7.

Description

Wafer defect detection method, equipment, medium and product Technical Field The application belongs to the technical field of semiconductor integrated circuits, and particularly relates to a wafer defect detection method, wafer defect detection equipment, wafer defect detection medium and wafer defect detection products. Background In integrated circuit fabrication, as process nodes continue to evolve, pattern size has approached physical limits and defect detection becomes critical. Scanning electron microscopes, such as defect review scanning electron microscopes (DEFECT REVIEW SCANNING Electron Microscope, DRSEM), can be used to scan wafers to identify defects, and are important wafer defect detection tools, and the accuracy and efficiency of the detection result are directly related to the improvement of the production yield and the positioning of the process problems. However, with the graph change caused by the process evolution, certain false defect misjudgment and defect omission detection still exist in the process of detecting the wafer defects at present. Therefore, how to improve the accuracy of wafer defect detection and avoid false defect misjudgment and defect missing detection becomes an important problem to be solved urgently. Disclosure of Invention The embodiment of the application provides a wafer defect detection method, equipment, a medium and a product, which can improve the accuracy of defect detection. According to a first aspect of the embodiment of the application, a wafer defect detection method is provided, which comprises the steps of carrying out defect scanning on a wafer to obtain a to-be-detected defect image of at least one to-be-detected defect position of the wafer, aligning the to-be-detected defect image with a chip design layout of the wafer to determine graphic features of the design layout graphic of the to-be-detected defect position, selecting a reference image generation model with adapted graphic features of the design layout graphic based on graphic feature conditions corresponding to a plurality of reference image generation models respectively, enabling different reference image generation models to correspond to different graphic feature conditions, converting the design layout graphic into a reference image based on the reference image generation model with adapted design layout graphic, and comparing the to-be-detected defect image of the to-be-detected defect position with the reference image to obtain a defect detection result. The second aspect of the embodiment of the application provides a wafer defect detection device, which comprises a scanning module, an alignment module, a selection module, a conversion module and a comparison module, wherein the scanning module is used for scanning defects of a wafer to obtain a defect image to be detected of at least one defect position to be detected of the wafer, the alignment module is used for aligning the defect image to be detected with a chip design layout of the wafer to determine graphic characteristics of the design layout graphic of the defect position to be detected, the selection module is used for selecting a reference image generation model with the graphic characteristics of the design layout graphic being adapted based on graphic characteristic conditions corresponding to a plurality of reference image generation models respectively, the different reference image generation models correspond to different graphic characteristic conditions, the conversion module is used for converting the design layout graphic into a reference image based on the reference image generation model with the design layout graphic being adapted, and the comparison module is used for comparing the defect image to be detected of the defect position to be detected with the reference image to obtain a defect detection result. In a third aspect of the embodiments of the present application, there is provided an electronic device, including a memory, and a program or an instruction stored in the memory and executable on a processor, the program or the instruction implementing the method for detecting a wafer defect according to any one of the embodiments of the present application when executed by the processor. In a fourth aspect of the embodiments of the present application, a readable storage medium is provided, where a program or an instruction is stored, where the program or the instruction implements the method for detecting a wafer defect according to any aspect of the embodiments of the present application when the program or the instruction is executed by a processor. In a fifth aspect of the embodiments of the present application, a computer program product is provided, where instructions in the computer program product, when executed by a processor of an electronic device, cause the electronic device to perform the method for detecting a wafer defect according to any one of the embodiments of the present applicati