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CN-122023328-A - Deep learning-based chip welding spot quality assessment method and system

CN122023328ACN 122023328 ACN122023328 ACN 122023328ACN-122023328-A

Abstract

The invention relates to the technical field of automatic detection of electronic manufacturing, and discloses a chip welding spot quality evaluation method and system based on deep learning, wherein the method comprises the following steps of: the method comprises the steps of obtaining an X-ray perspective image of a printed circuit board assembly and an electronic design automation design file, completing coordinate registration, constructing a multi-mode graph node containing visual, spatial and physical semantic features, constructing a heterogeneous topological graph containing a homogeneous adjacent side, a heterogeneous adjacent side and a long Cheng Luansheng side according to the heat capacity function type and physical distribution of welding spots, carrying out feature aggregation by using a graph annotation force network introducing a heat capacity semantic bias term, correcting weight deviation caused by heat capacity difference, inputting the updated features into a double-branch judgment module, and dynamically adjusting a judgment threshold value of local defect classification by using a warping risk coefficient based on full graph symmetry. The invention effectively solves the quality misjudgment problem caused by different welding spot heat dissipation conditions and package warpage, and improves the robustness and accuracy of detection.

Inventors

  • LU JINFA

Assignees

  • 江西安芯美科技有限公司

Dates

Publication Date
20260512
Application Date
20260129

Claims (10)

  1. 1. The chip welding spot quality evaluation method based on deep learning is characterized by comprising the following steps of: S100, acquiring an X-ray perspective image and an electronic design automation design file of a printed circuit board assembly, and calculating and completing registration of image pixel coordinates and physical design coordinates; S200, establishing a welding point diagram node based on a registration result, and extracting visual, spatial and physical semantic features to splice into an initial feature representation; S300, constructing an isomerism topological graph according to the function type and physical distribution of the heat capacity of the welding spots, wherein the isomerism topological graph comprises a homogeneous adjacent side, a heterogeneous adjacent side and a long Cheng Luansheng side; S400, inputting the heterogeneous topological graph into a graph attention network, introducing a heat capacity semantic bias item according to a connection edge type to correct attention weight coefficients, and acquiring updated node characteristic representation based on the corrected attention weight coefficients in a polymerization way; S500, inputting the updated node characteristic representation into a double-branch judgment module, generating a warping risk coefficient by utilizing the characteristic distance of the nodes at the two ends of the long Cheng Luansheng side, dynamically adjusting the judgment threshold value of the local defect classification branch according to the warping risk coefficient, and outputting a chip welding spot quality evaluation result.
  2. 2. The deep learning-based chip solder joint quality evaluation method according to claim 1, wherein the specific process of calculating the mapping relationship and registration in step S100 includes: searching theoretical physical coordinates of a preset reference mark point in the electronic design automation design file, and positioning image pixel center coordinates of the corresponding reference mark point in the X-ray perspective image; constructing a source point set and a target point set which comprise a plurality of reference mark points; Establishing a two-dimensional affine transformation model containing translation, rotation and scaling factors, constructing a loss function taking the square sum of coordinate transformation errors as a target, and solving a globally optimal affine transformation matrix by using a least square method; And mapping theoretical physical coordinates of all welding spots in the electronic design automation design file into image pixel coordinates by utilizing the affine transformation matrix, and binding network connection attributes analyzed from the electronic design automation design file with the mapped image pixel coordinates.
  3. 3. The deep learning-based chip solder joint quality evaluation method according to claim 1, wherein the multi-modal feature extraction process in step S200 includes: Intercepting an interested region image taking the physical center of a welding spot as an origin on the X-ray perspective image, normalizing the interested region image, inputting the normalized interested region image into a backbone network of a convolutional neural network, and extracting the output of a global average pooling layer as the visual feature vector; calculating the relative offset and Euclidean distance of a welding spot relative to the geometric center of the chip, normalizing the welding spot, inputting the normalized welding spot into a multi-layer perceptron position encoder, and mapping the normalized welding spot to obtain the spatial position feature vector; analyzing network connection attributes in the electronic design automation design file, and dividing welding spots into discrete heat capacity function types according to the electric network functions and the copper foil areas of the welding spot connection; and searching a row vector corresponding to the heat capacity function type in a preset entity embedding matrix to obtain the physical semantic feature vector.
  4. 4. The deep learning-based chip solder joint quality evaluation method according to claim 1, wherein the specific process of constructing the neighboring connection edges and the division types in step S300 includes: calculating Euclidean distances among physical coordinates of all welding spots on the chip, and establishing a neighbor connection edge between two welding spot nodes of which the Euclidean distances are smaller than a preset heat influence radius threshold; retrieving heat capacity function types of two welding spot nodes for establishing the adjacent connecting edges; If the welding spots at the two ends of the connecting edge have the same heat capacity function type, marking the adjacent connecting edge as the homogeneous adjacent edge; and if the welding spots at the two ends of the connecting edge have different heat capacity function types, marking the adjacent connecting edge as the heterogeneous adjacent edge.
  5. 5. The deep learning-based chip solder joint quality evaluation method according to claim 4, wherein the specific process of constructing the long Cheng Luansheng sides in the step S300 includes: calculating the coordinates of a geometric center point of the chip package, traversing each welding spot node, and calculating the theoretical symmetrical coordinates of each welding spot node about the geometric center point; Searching target nodes with physical coordinates matched with the theoretical symmetrical coordinates in all welding spot nodes, judging that two welding spot nodes are twin node pairs if the central symmetrical error of the two welding spot nodes is smaller than a preset space tolerance threshold, establishing undirected connecting edges between the twin node pairs, and marking the undirected connecting edges as long Cheng Luansheng edges.
  6. 6. The deep learning-based chip solder joint quality evaluation method according to claim 1, wherein the specific process of introducing the heat capacity semantic bias term in step S400 comprises: initializing a group of learnable bias parameter sets, wherein the bias parameter sets comprise bias values respectively corresponding to the homogeneous adjacent side, the heterogeneous adjacent side and the long Cheng Luansheng side; for any connecting edge in the heterogeneous topological graph, identifying the type of the connecting edge, and loading a corresponding heat capacity semantic bias value from the bias parameter set; the offset value corresponding to the heterogeneous adjacent side is used for compensating imaging gray scale difference caused by different heat capacity function types, and the offset value corresponding to the long Cheng Luansheng side is used for strengthening characteristic association weight of the geometrical symmetric position of the chip.
  7. 7. The deep learning-based chip solder joint quality evaluation method according to claim 6, wherein the specific process of calculating the attention weight coefficient in step S400 includes: Performing dimension reduction mapping on the initial characteristic representation of the graph nodes by using the shared linear transformation matrix; for a target node and any one neighbor node thereof, splicing the transformed feature vectors, and performing dot product operation with the attention weight vector to obtain an original relevance score; And directly superposing the heat capacity semantic bias value corresponding to the connection edge type on the original correlation score, and executing nonlinear activation operation and exponential normalization operation on the superposed result to obtain a corrected attention weight coefficient.
  8. 8. The deep learning-based chip solder joint quality evaluation method according to claim 1, wherein the specific process of step S500 includes: Constructing a local defect classification module comprising a full connection layer, mapping the updated node characteristic representation to a preset defect class space, and outputting basic probability distribution of each welding spot belonging to each defect class; Constructing global symmetry consistency branches, traversing the twin node pairs connected by the long Cheng Luansheng edges, and calculating Euclidean distance of the twin node pairs in a feature space; And mapping the Euclidean distance into a numerical value with a value between zero and one by using a nonlinear mapping function, wherein the larger the Euclidean distance is, the higher the warpage risk coefficient is.
  9. 9. The deep learning-based chip solder joint quality evaluation method according to claim 8, wherein the specific process of dynamically adjusting the decision threshold in step S500 includes: setting a basic decision threshold and a sensitivity adjustment factor for defect types sensitive to coplanarity; Calculating the product among the sensitivity adjustment factor, the warping risk coefficient and the complement of the basic probability that the welding spot is judged to be in a normal category; and calculating the ratio of the probability value of each defect category in the basic probability distribution to the corresponding dynamic judgment threshold value, and selecting the category with the largest ratio as a final chip welding spot quality evaluation result.
  10. 10. The deep learning-based chip solder joint quality evaluation system applied to the deep learning-based chip solder joint quality evaluation method of any one of claims 1 to 9, comprising: The data acquisition and registration module is used for acquiring an X-ray perspective image of the printed circuit board assembly and an electronic design automation design file, and calculating the registration relation between image pixel coordinates and physical design coordinates; the multi-mode feature extraction module is used for extracting visual feature vectors, spatial position feature vectors and physical semantic feature vectors of welding spots and generating initial feature representations of the graph nodes; The heterogram construction module is used for constructing an isomerism topological graph comprising a homogeneous adjacent side, a heterogeneous adjacent side and a long Cheng Luansheng side according to the physical distribution of welding spots and the heat capacity function type; the diagram attention aggregation module is used for introducing a heat capacity semantic bias item corresponding to the edge type into the diagram attention network and updating node characteristics based on the corrected attention weight; and the double-branch cooperative judgment module is used for generating quality class probability by utilizing the local defect classification branches, generating warping risk coefficients by utilizing the global symmetry consistency branches, and dynamically adjusting judgment threshold values based on the warping risk coefficients to output an evaluation result.

Description

Deep learning-based chip welding spot quality assessment method and system Technical Field The invention relates to the technical field of electronic manufacturing automation detection, in particular to a chip welding spot quality assessment method and system based on deep learning. Background With the development of electronic assembly technology toward high density and miniaturization, ball Grid Array (BGA) and Chip Scale Package (CSP) devices have been widely used in printed circuit board assemblies. Because the welding spots in the packaging form are positioned below the chip body, the welding quality of the traditional automatic optical detection equipment cannot be directly observed, so that the automatic X-ray detection equipment utilizing the X-ray transmission imaging technology becomes a main detection means. The existing automatic X-ray detection technology mainly relies on computer vision algorithm to analyze the welding spot image. In the early detection method, based on the rule of manual design, geometric parameters such as the projected area, roundness, contrast and the like of a welding spot are calculated, and a fixed threshold range is set to judge whether defects such as cold joint, tin connection or cavity exist. However, this rule-based approach is sensitive to imaging noise and, in the face of complex and varying circuit board wiring backgrounds, it is difficult to extract robust features, resulting in high false alarm rates. In recent years, deep learning techniques typified by convolutional neural networks have improved the accuracy of solder joint defect detection. Such methods typically take as input a local image of a single weld spot, automatically extract features and classify using a neural network. However, this approach often treats each bond pad on the die as a separate individual from each other, ignoring the physical associations and process logic that exist between bond pads. In practice, the die pads are not isolated, they are interconnected by copper foil traces within the circuit board, and are subject to a common thermal environment during the reflow process. Disclosure of Invention Aiming at the defects of the prior art, the invention provides a chip welding spot quality evaluation method and a chip welding spot quality evaluation system based on deep learning, which solve the problems that the conventional X-ray detection technology ignores the welding spot heat capacity attribute and the packaging geometric deformation characteristic, so that the normal process gray level fluctuation and the real defect cannot be distinguished, and the warpage related defect is difficult to identify by utilizing the global topological relation. In order to achieve the purpose, the invention is realized by the following technical scheme that the chip welding spot quality assessment method based on deep learning comprises the following steps: S100, acquiring an X-ray perspective image and an electronic design automation design file of a printed circuit board assembly, and calculating and completing registration of image pixel coordinates and physical design coordinates; S200, establishing a welding point diagram node based on a registration result, and extracting visual, spatial and physical semantic features to splice into an initial feature representation; S300, constructing an isomerism topological graph according to the function type and physical distribution of the heat capacity of the welding spots, wherein the isomerism topological graph comprises a homogeneous adjacent side, a heterogeneous adjacent side and a long Cheng Luansheng side; S400, inputting the heterogeneous topological graph into a graph attention network, introducing a heat capacity semantic bias item according to a connection edge type to correct attention weight coefficients, and acquiring updated node characteristic representation based on the corrected attention weight coefficients in a polymerization way; S500, inputting the updated node characteristic representation into a double-branch judgment module, generating a warping risk coefficient by utilizing the characteristic distance of the nodes at the two ends of the long Cheng Luansheng side, dynamically adjusting the judgment threshold value of the local defect classification branch according to the warping risk coefficient, and outputting a chip welding spot quality evaluation result. Preferably, the specific process of calculating the mapping relationship and registering in step S100 includes: searching theoretical physical coordinates of a preset reference mark point in the electronic design automation design file, and positioning image pixel center coordinates of the corresponding reference mark point in the X-ray perspective image; constructing a source point set and a target point set which comprise a plurality of reference mark points; Establishing a two-dimensional affine transformation model containing translation, rotation and scaling factors,